6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-12 01:25:49 +00:00
Code Issues Projects Releases Wiki Activity

Implement MaskedValueIsZero for ANY_EXTEND nodes

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25900 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-02-02 06:43:15 +00:00
parent 1bac941019
commit 9a06cce0f2
1 changed files with 5 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@@ -154,6 +154,11 @@ bool TargetLowering::MaskedValueIsZero(const SDOperand &Op,
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits))); return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)));
case ISD::ANY_EXTEND:
// If the mask only includes bits in the low part, recurse.
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
if (Mask >> SrcBits) return false; // Use of unknown top bits.
return MaskedValueIsZero(Op.getOperand(0), Mask);
case ISD::AssertZext: case ISD::AssertZext:
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.