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Add a separate ARM instruction format for Saturate instructions.

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(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-11 00:01:18 +00:00
parent 0a16b22e64
commit 9a1c189d9e
7 changed files with 205 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -98,44 +98,45 @@ namespace ARMII {
// Miscellaneous arithmetic instructions
ArithMiscFrm = 12 << FormShift,
SatFrm = 13 << FormShift,
// Extend instructions
ExtFrm = 13 << FormShift,
ExtFrm = 14 << FormShift,
// VFP formats
VFPUnaryFrm = 14 << FormShift,
VFPBinaryFrm = 15 << FormShift,
VFPConv1Frm = 16 << FormShift,
VFPConv2Frm = 17 << FormShift,
VFPConv3Frm = 18 << FormShift,
VFPConv4Frm = 19 << FormShift,
VFPConv5Frm = 20 << FormShift,
VFPLdStFrm = 21 << FormShift,
VFPLdStMulFrm = 22 << FormShift,
VFPMiscFrm = 23 << FormShift,
VFPUnaryFrm = 15 << FormShift,
VFPBinaryFrm = 16 << FormShift,
VFPConv1Frm = 17 << FormShift,
VFPConv2Frm = 18 << FormShift,
VFPConv3Frm = 19 << FormShift,
VFPConv4Frm = 20 << FormShift,
VFPConv5Frm = 21 << FormShift,
VFPLdStFrm = 22 << FormShift,
VFPLdStMulFrm = 23 << FormShift,
VFPMiscFrm = 24 << FormShift,
// Thumb format
ThumbFrm = 24 << FormShift,
ThumbFrm = 25 << FormShift,
// Miscelleaneous format
MiscFrm = 25 << FormShift,
MiscFrm = 26 << FormShift,
// NEON formats
NGetLnFrm = 26 << FormShift,
NSetLnFrm = 27 << FormShift,
NDupFrm = 28 << FormShift,
NLdStFrm = 29 << FormShift,
N1RegModImmFrm= 30 << FormShift,
N2RegFrm = 31 << FormShift,
NVCVTFrm = 32 << FormShift,
NVDupLnFrm = 33 << FormShift,
N2RegVShLFrm = 34 << FormShift,
N2RegVShRFrm = 35 << FormShift,
N3RegFrm = 36 << FormShift,
N3RegVShFrm = 37 << FormShift,
NVExtFrm = 38 << FormShift,
NVMulSLFrm = 39 << FormShift,
NVTBLFrm = 40 << FormShift,
NGetLnFrm = 27 << FormShift,
NSetLnFrm = 28 << FormShift,
NDupFrm = 29 << FormShift,
NLdStFrm = 30 << FormShift,
N1RegModImmFrm= 31 << FormShift,
N2RegFrm = 32 << FormShift,
NVCVTFrm = 33 << FormShift,
NVDupLnFrm = 34 << FormShift,
N2RegVShLFrm = 35 << FormShift,
N2RegVShRFrm = 36 << FormShift,
N3RegFrm = 37 << FormShift,
N3RegVShFrm = 38 << FormShift,
NVExtFrm = 39 << FormShift,
NVMulSLFrm = 40 << FormShift,
NVTBLFrm = 41 << FormShift,
//===------------------------------------------------------------------===//
// Misc flags.

45
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -124,6 +124,8 @@ namespace {
void emitMiscArithInstruction(const MachineInstr &MI);
void emitSaturateInstruction(const MachineInstr &MI);
void emitBranchInstruction(const MachineInstr &MI);
void emitInlineJumpTable(unsigned JTIndex);
@ -389,6 +391,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
case ARMII::ArithMiscFrm:
emitMiscArithInstruction(MI);
break;
case ARMII::SatFrm:
emitSaturateInstruction(MI);
break;
case ARMII::BrFrm:
emitBranchInstruction(MI);
break;
@ -1228,6 +1233,46 @@ void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
emitWordLE(Binary);
}
void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();
// Part of binary is determined by TableGen.
unsigned Binary = getBinaryCodeForInstr(MI);
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
// Encode Rd
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
// Encode saturate bit position.
unsigned Pos = MI.getOperand(1).getImm();
if (TID.Opcode == ARM::SSATlsl ||
TID.Opcode == ARM::SSATasr ||
TID.Opcode == ARM::SSAT16)
Pos -= 1;
assert((Pos < 16 || (Pos < 32 &&
TID.Opcode != ARM::SSAT16 &&
TID.Opcode != ARM::USAT16)) &&
"saturate bit position out of range");
Binary |= Pos << 16;
// Encode Rm
Binary |= getMachineOpValue(MI, 2);
// Encode shift_imm.
if (TID.getNumOperands() == 4) {
unsigned ShiftAmt = MI.getOperand(3).getImm();
if (ShiftAmt == 32 &&
(TID.Opcode == ARM::SSATasr || TID.Opcode == ARM::USATasr))
ShiftAmt = 0;
assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
Binary |= ShiftAmt << ARMII::ShiftShift;
}
emitWordLE(Binary);
}
void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
const TargetInstrDesc &TID = MI.getDesc();

57
lib/Target/ARM/ARMInstrFormats.td
View File

@ -36,37 +36,38 @@ def LdStMulFrm : Format<10>;
def LdStExFrm : Format<11>;
def ArithMiscFrm : Format<12>;
def ExtFrm : Format<13>;
def SatFrm : Format<13>;
def ExtFrm : Format<14>;
def VFPUnaryFrm : Format<14>;
def VFPBinaryFrm : Format<15>;
def VFPConv1Frm : Format<16>;
def VFPConv2Frm : Format<17>;
def VFPConv3Frm : Format<18>;
def VFPConv4Frm : Format<19>;
def VFPConv5Frm : Format<20>;
def VFPLdStFrm : Format<21>;
def VFPLdStMulFrm : Format<22>;
def VFPMiscFrm : Format<23>;
def VFPUnaryFrm : Format<15>;
def VFPBinaryFrm : Format<16>;
def VFPConv1Frm : Format<17>;
def VFPConv2Frm : Format<18>;
def VFPConv3Frm : Format<19>;
def VFPConv4Frm : Format<20>;
def VFPConv5Frm : Format<21>;
def VFPLdStFrm : Format<22>;
def VFPLdStMulFrm : Format<23>;
def VFPMiscFrm : Format<24>;
def ThumbFrm : Format<24>;
def MiscFrm : Format<25>;
def ThumbFrm : Format<25>;
def MiscFrm : Format<26>;
def NGetLnFrm : Format<26>;
def NSetLnFrm : Format<27>;
def NDupFrm : Format<28>;
def NLdStFrm : Format<29>;
def N1RegModImmFrm: Format<30>;
def N2RegFrm : Format<31>;
def NVCVTFrm : Format<32>;
def NVDupLnFrm : Format<33>;
def N2RegVShLFrm : Format<34>;
def N2RegVShRFrm : Format<35>;
def N3RegFrm : Format<36>;
def N3RegVShFrm : Format<37>;
def NVExtFrm : Format<38>;
def NVMulSLFrm : Format<39>;
def NVTBLFrm : Format<40>;
def NGetLnFrm : Format<27>;
def NSetLnFrm : Format<28>;
def NDupFrm : Format<29>;
def NLdStFrm : Format<30>;
def N1RegModImmFrm: Format<31>;
def N2RegFrm : Format<32>;
def NVCVTFrm : Format<33>;
def NVDupLnFrm : Format<34>;
def N2RegVShLFrm : Format<35>;
def N2RegVShRFrm : Format<36>;
def N3RegFrm : Format<37>;
def N3RegVShFrm : Format<38>;
def NVExtFrm : Format<39>;
def NVMulSLFrm : Format<40>;
def NVTBLFrm : Format<41>;
// Misc flags.

16
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1810,20 +1810,22 @@ def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
// Signed/Unsigned saturate -- for disassembly only
def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
SatFrm, NoItinerary,
"ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-21} = 0b0110101;
let Inst{6-4} = 0b001;
}
def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
SatFrm, NoItinerary,
"ssat", "\t$dst, $bit_pos, $a, asr $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-21} = 0b0110101;
let Inst{6-4} = 0b101;
}
def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-20} = 0b01101010;
@ -1831,20 +1833,22 @@ def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
}
def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
SatFrm, NoItinerary,
"usat", "\t$dst, $bit_pos, $a, lsl $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-21} = 0b0110111;
let Inst{6-4} = 0b001;
}
def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
SatFrm, NoItinerary,
"usat", "\t$dst, $bit_pos, $a, asr $shamt",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-21} = 0b0110111;
let Inst{6-4} = 0b101;
}
def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
[/* For disassembly only; pattern left blank */]> {
let Inst{27-20} = 0b01101110;

90
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -908,34 +908,6 @@ static inline bool getBFCInvMask(uint32_t insn, uint32_t &mask) {
return true;
}
static inline bool SaturateOpcode(unsigned Opcode) {
switch (Opcode) {
case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
return true;
default:
return false;
}
}
static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
switch (Opcode) {
case ARM::SSATlsl:
case ARM::SSATasr:
return slice(insn, 20, 16) + 1;
case ARM::SSAT16:
return slice(insn, 19, 16) + 1;
case ARM::USATlsl:
case ARM::USATasr:
return slice(insn, 20, 16);
case ARM::USAT16:
return slice(insn, 19, 16);
default:
assert(0 && "Invalid opcode passed in");
return 0;
}
}
// A major complication is the fact that some of the saturating add/subtract
// operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
// They are QADD, QDADD, QDSUB, and QSUB.
@ -961,34 +933,6 @@ static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (OpIdx >= NumOps)
return false;
// SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
if (SaturateOpcode(Opcode)) {
MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
OpIdx += 2;
return true;
}
// For SSAT operand reg (Rm) has been disassembled above.
// Now disassemble the shift amount.
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 11, 7);
// A8.6.183. Possible ASR shift amount of 32...
if (Opcode == ARM::SSATasr && ShAmt == 0)
ShAmt = 32;
MI.addOperand(MCOperand::CreateImm(ShAmt));
OpIdx += 3;
return true;
}
// Special-case handling of BFC/BFI/SBFX/UBFX.
if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
MI.addOperand(MCOperand::CreateReg(0));
@ -1509,6 +1453,39 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return true;
}
/// DisassembleSatFrm - Disassemble saturate instructions:
/// SSAT, SSAT16, USAT, and USAT16.
static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
const TargetInstrDesc &TID = ARMInsts[Opcode];
NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
// Disassemble register def.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRd(insn))));
unsigned Pos = slice(insn, 20, 16);
if (Opcode == ARM::SSATlsl ||
Opcode == ARM::SSATasr ||
Opcode == ARM::SSAT16)
Pos += 1;
MI.addOperand(MCOperand::CreateImm(Pos));
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
if (NumOpsAdded == 4) {
// Inst{11-7} encodes the imm5 shift amount.
unsigned ShAmt = slice(insn, 11, 7);
// A8.6.183. Possible ASR shift amount of 32...
if ((Opcode == ARM::SSATasr || Opcode == ARM::USATasr) && ShAmt == 0)
ShAmt = 32;
MI.addOperand(MCOperand::CreateImm(ShAmt));
}
return true;
}
// Extend instructions.
// SXT* and UXT*: Rd [Rn] Rm [rot_imm].
// The 2nd operand register is Rn and the 3rd operand regsiter is Rm for the
@ -3085,6 +3062,7 @@ static const DisassembleFP FuncPtrs[] = {
&DisassembleLdStMulFrm,
&DisassembleLdStExFrm,
&DisassembleArithMiscFrm,
&DisassembleSatFrm,
&DisassembleExtFrm,
&DisassembleVFPUnaryFrm,
&DisassembleVFPBinaryFrm,

59
lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
View File

@ -54,36 +54,35 @@ public:
ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
ENTRY(ARM_FORMAT_EXTFRM, 13) \
ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
ENTRY(ARM_FORMAT_THUMBFRM, 24) \
ENTRY(ARM_FORMAT_NEONFRM, 25) \
ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
ENTRY(ARM_FORMAT_MISCFRM, 29) \
ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
ENTRY(ARM_FORMAT_NLdSt, 31) \
ENTRY(ARM_FORMAT_N1RegModImm, 32) \
ENTRY(ARM_FORMAT_N2Reg, 33) \
ENTRY(ARM_FORMAT_NVCVT, 34) \
ENTRY(ARM_FORMAT_NVecDupLn, 35) \
ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
ENTRY(ARM_FORMAT_N3Reg, 38) \
ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
ENTRY(ARM_FORMAT_NVecExtract, 40) \
ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
ENTRY(ARM_FORMAT_NVTBL, 42)
ENTRY(ARM_FORMAT_SATFRM, 13) \
ENTRY(ARM_FORMAT_EXTFRM, 14) \
ENTRY(ARM_FORMAT_VFPUNARYFRM, 15) \
ENTRY(ARM_FORMAT_VFPBINARYFRM, 16) \
ENTRY(ARM_FORMAT_VFPCONV1FRM, 17) \
ENTRY(ARM_FORMAT_VFPCONV2FRM, 18) \
ENTRY(ARM_FORMAT_VFPCONV3FRM, 19) \
ENTRY(ARM_FORMAT_VFPCONV4FRM, 20) \
ENTRY(ARM_FORMAT_VFPCONV5FRM, 21) \
ENTRY(ARM_FORMAT_VFPLDSTFRM, 22) \
ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 23) \
ENTRY(ARM_FORMAT_VFPMISCFRM, 24) \
ENTRY(ARM_FORMAT_THUMBFRM, 25) \
ENTRY(ARM_FORMAT_MISCFRM, 26) \
ENTRY(ARM_FORMAT_NEONGETLNFRM, 27) \
ENTRY(ARM_FORMAT_NEONSETLNFRM, 28) \
ENTRY(ARM_FORMAT_NEONDUPFRM, 29) \
ENTRY(ARM_FORMAT_NLdSt, 30) \
ENTRY(ARM_FORMAT_N1RegModImm, 31) \
ENTRY(ARM_FORMAT_N2Reg, 32) \
ENTRY(ARM_FORMAT_NVCVT, 33) \
ENTRY(ARM_FORMAT_NVecDupLn, 34) \
ENTRY(ARM_FORMAT_N2RegVecShL, 35) \
ENTRY(ARM_FORMAT_N2RegVecShR, 36) \
ENTRY(ARM_FORMAT_N3Reg, 37) \
ENTRY(ARM_FORMAT_N3RegVecSh, 38) \
ENTRY(ARM_FORMAT_NVecExtract, 39) \
ENTRY(ARM_FORMAT_NVecMulScalar, 40) \
ENTRY(ARM_FORMAT_NVTBL, 41)
// ARM instruction format specifies the encoding used by the instruction.
#define ENTRY(n, v) n = v,

59
utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -49,36 +49,35 @@ using namespace llvm;
ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
ENTRY(ARM_FORMAT_EXTFRM, 13) \
ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
ENTRY(ARM_FORMAT_THUMBFRM, 24) \
ENTRY(ARM_FORMAT_NEONFRM, 25) \
ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
ENTRY(ARM_FORMAT_MISCFRM, 29) \
ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
ENTRY(ARM_FORMAT_NLdSt, 31) \
ENTRY(ARM_FORMAT_N1RegModImm, 32) \
ENTRY(ARM_FORMAT_N2Reg, 33) \
ENTRY(ARM_FORMAT_NVCVT, 34) \
ENTRY(ARM_FORMAT_NVecDupLn, 35) \
ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
ENTRY(ARM_FORMAT_N3Reg, 38) \
ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
ENTRY(ARM_FORMAT_NVecExtract, 40) \
ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
ENTRY(ARM_FORMAT_NVTBL, 42)
ENTRY(ARM_FORMAT_SATFRM, 13) \
ENTRY(ARM_FORMAT_EXTFRM, 14) \
ENTRY(ARM_FORMAT_VFPUNARYFRM, 15) \
ENTRY(ARM_FORMAT_VFPBINARYFRM, 16) \
ENTRY(ARM_FORMAT_VFPCONV1FRM, 17) \
ENTRY(ARM_FORMAT_VFPCONV2FRM, 18) \
ENTRY(ARM_FORMAT_VFPCONV3FRM, 19) \
ENTRY(ARM_FORMAT_VFPCONV4FRM, 20) \
ENTRY(ARM_FORMAT_VFPCONV5FRM, 21) \
ENTRY(ARM_FORMAT_VFPLDSTFRM, 22) \
ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 23) \
ENTRY(ARM_FORMAT_VFPMISCFRM, 24) \
ENTRY(ARM_FORMAT_THUMBFRM, 25) \
ENTRY(ARM_FORMAT_MISCFRM, 26) \
ENTRY(ARM_FORMAT_NEONGETLNFRM, 27) \
ENTRY(ARM_FORMAT_NEONSETLNFRM, 28) \
ENTRY(ARM_FORMAT_NEONDUPFRM, 29) \
ENTRY(ARM_FORMAT_NLdSt, 30) \
ENTRY(ARM_FORMAT_N1RegModImm, 31) \
ENTRY(ARM_FORMAT_N2Reg, 32) \
ENTRY(ARM_FORMAT_NVCVT, 33) \
ENTRY(ARM_FORMAT_NVecDupLn, 34) \
ENTRY(ARM_FORMAT_N2RegVecShL, 35) \
ENTRY(ARM_FORMAT_N2RegVecShR, 36) \
ENTRY(ARM_FORMAT_N3Reg, 37) \
ENTRY(ARM_FORMAT_N3RegVecSh, 38) \
ENTRY(ARM_FORMAT_NVecExtract, 39) \
ENTRY(ARM_FORMAT_NVecMulScalar, 40) \
ENTRY(ARM_FORMAT_NVTBL, 41)
// ARM instruction format specifies the encoding used by the instruction.
#define ENTRY(n, v) n = v,