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Emit correct code when making a ConstantPool entry for a vector
constant whose component type is not a legal type for the target. (If the target ConstantPool cannot handle this type either, it has an opportunity to merge elements. In practice any target with 8-bit bytes must support i8 *as data*). 7320806 (partial). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86751 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1813,10 +1813,19 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
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} else if (ConstantSDNode *V =
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dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
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CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
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if (OpVT==EltVT)
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CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
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else {
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// If OpVT and EltVT don't match, EltVT is not legal and the
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// element values have been promoted/truncated earlier. Undo this;
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// we don't want a v16i8 to become a v16i32 for example.
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const ConstantInt *CI = V->getConstantIntValue();
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CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
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CI->getZExtValue()));
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}
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} else {
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assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
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const Type *OpNTy = OpVT.getTypeForEVT(*DAG.getContext());
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const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
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CV.push_back(UndefValue::get(OpNTy));
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}
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}
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36
test/CodeGen/PowerPC/vec_auto_constant.ll
Normal file
36
test/CodeGen/PowerPC/vec_auto_constant.ll
Normal file
@ -0,0 +1,36 @@
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; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
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; Formerly produced .long, 7320806 (partial)
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; CHECK: .byte 22
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; CHECK: .byte 21
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; CHECK: .byte 20
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; CHECK: .byte 3
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; CHECK: .byte 25
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; CHECK: .byte 24
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; CHECK: .byte 23
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; CHECK: .byte 3
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; CHECK: .byte 28
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; CHECK: .byte 27
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; CHECK: .byte 26
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; CHECK: .byte 3
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; CHECK: .byte 31
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; CHECK: .byte 30
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; CHECK: .byte 29
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; CHECK: .byte 3
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@baz = common global <16 x i8> zeroinitializer ; <<16 x i8>*> [#uses=1]
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define void @foo(<16 x i8> %x) nounwind ssp {
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entry:
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%x_addr = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
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%temp = alloca <16 x i8> ; <<16 x i8>*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store <16 x i8> %x, <16 x i8>* %x_addr
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store <16 x i8> <i8 22, i8 21, i8 20, i8 3, i8 25, i8 24, i8 23, i8 3, i8 28, i8 27, i8 26, i8 3, i8 31, i8 30, i8 29, i8 3>, <16 x i8>* %temp, align 16
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%0 = load <16 x i8>* %x_addr, align 16 ; <<16 x i8>> [#uses=1]
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%1 = load <16 x i8>* %temp, align 16 ; <<16 x i8>> [#uses=1]
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%tmp = add <16 x i8> %0, %1 ; <<16 x i8>> [#uses=1]
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store <16 x i8> %tmp, <16 x i8>* @baz, align 16
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br label %return
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return: ; preds = %entry
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ret void
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}
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