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Remove a few more calls to TargetMachine::getSubtarget from the

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R600 port.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229804 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2015-02-19 01:10:55 +00:00
parent fde0733828
commit 9a6b4219e2
2 changed files with 4 additions and 4 deletions
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2
lib/Target/R600/R600MachineScheduler.cpp
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@@ -26,7 +26,7 @@ using namespace llvm;
void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
DAG = static_cast<ScheduleDAGMILive*>(dag); DAG = static_cast<ScheduleDAGMILive*>(dag);
const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = DAG->MF.getSubtarget<AMDGPUSubtarget>();
TII = static_cast<const R600InstrInfo*>(DAG->TII); TII = static_cast<const R600InstrInfo*>(DAG->TII);
TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
VLIW5 = !ST.hasCaymanISA(); VLIW5 = !ST.hasCaymanISA();

6
lib/Target/R600/SIMachineFunctionInfo.cpp
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@@ -39,8 +39,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
unsigned FrameIndex, unsigned FrameIndex,
unsigned SubIdx) { unsigned SubIdx) {
const MachineFrameInfo *FrameInfo = MF->getFrameInfo(); const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>( const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
MF->getTarget().getSubtarget<AMDGPUSubtarget>().getRegisterInfo()); MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
int64_t Offset = FrameInfo->getObjectOffset(FrameIndex); int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
Offset += SubIdx * 4; Offset += SubIdx * 4;
@@ -70,7 +70,7 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize( unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
const MachineFunction &MF) const { const MachineFunction &MF) const {
const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
// FIXME: We should get this information from kernel attributes if it // FIXME: We should get this information from kernel attributes if it
// is available. // is available.
return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize(); return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();