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[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith 2014-04-09 14:44:07 +00:00
parent 86c067813c
commit 9a9fa81c1a
2 changed files with 4 additions and 2 deletions
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4
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
View File

@ -2001,7 +2001,7 @@ static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
Inst.addOperand(MCOperand::CreateImm(index)); Inst.addOperand(MCOperand::CreateImm(index));
} }
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM64::ST1i8_POST: case ARM64::ST1i8_POST:
@ -2162,7 +2162,7 @@ static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
} }
Inst.addOperand(MCOperand::CreateImm(index)); Inst.addOperand(MCOperand::CreateImm(index));
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) { switch (Inst.getOpcode()) {
case ARM64::LD1i8_POST: case ARM64::LD1i8_POST:

2
test/MC/Disassembler/ARM64/advsimd.txt
View File

@ -618,6 +618,7 @@
0x0a 0x68 0x40 0x4c 0x0a 0x68 0x40 0x4c
0x2d 0xac 0x40 0x0c 0x2d 0xac 0x40 0x0c
0x4f 0x7c 0x40 0x4c 0x4f 0x7c 0x40 0x4c
0xe0 0x03 0x40 0x0d
# CHECK: ld1.8b { v1 }, [x1] # CHECK: ld1.8b { v1 }, [x1]
# CHECK: ld1.16b { v2, v3 }, [x2] # CHECK: ld1.16b { v2, v3 }, [x2]
@ -627,6 +628,7 @@
# CHECK: ld1.4s { v10, v11, v12 }, [x0] # CHECK: ld1.4s { v10, v11, v12 }, [x0]
# CHECK: ld1.1d { v13, v14 }, [x1] # CHECK: ld1.1d { v13, v14 }, [x1]
# CHECK: ld1.2d { v15 }, [x2] # CHECK: ld1.2d { v15 }, [x2]
# CHECK: ld1.b { v0 }[0], [sp]
0x41 0x70 0xdf 0x0c 0x41 0x70 0xdf 0x0c
0x41 0xa0 0xdf 0x0c 0x41 0xa0 0xdf 0x0c