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Increase opportunities to optimize (brcond (srl (and c1), c2)).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91717 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-12-18 21:31:31 +00:00
parent 3eed182e2d
commit 9ab2b98ba5
2 changed files with 57 additions and 1 deletions
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29
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -2755,7 +2755,34 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
if (N1C) {
SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
if (NewSRL.getNode())
return NewSRL;
}
// Here is a common situation. We want to optimize:
//
// %a = ...
// %b = and i32 %a, 2
// %c = srl i32 %b, 1
// brcond i32 %c ...
//
// into
//
// %a = ...
// %b = and %a, 2
// %c = setcc eq %b, 0
// brcond %c ...
//
// However when after the source operand of SRL is optimized into AND, the SRL
// itself may not be optimized further. Look for it and add the BRCOND into
// the worklist.
if (N->hasOneUse() &&
N->use_begin()->getOpcode() == ISD::BRCOND)
AddToWorkList(*N->use_begin());
return SDValue();
}
SDValue DAGCombiner::visitCTLZ(SDNode *N) {