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No need for ccop anymore.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37965 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-06 23:34:09 +00:00
parent d2c5eb864f
commit 9ad6f03166
3 changed files with 17 additions and 23 deletions
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20
lib/Target/ARM/ARMInstrInfo.td
View File

@ -286,12 +286,6 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
let PrintMethod = "printPredicateOperand";
}
// Conditional code operand for conditional branches and conditional moves.
// No AlwaysVal value.
def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
let PrintMethod = "printPredicateOperand";
}
// Conditional code result for instructions whose 's' bit is set, e.g. subs.
//
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
@ -702,7 +696,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
def Bcc : AI<(ops brtarget:$dst), "b", " $dst",
[/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
}
@ -1192,18 +1186,18 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
// Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
"mov$cc $dst, $true",
def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
"mov$cc $dst, $true",
def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
"mov$cc $dst, $true",
def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true),
"mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;

4
lib/Target/ARM/ARMInstrThumb.td
View File

@ -226,7 +226,7 @@ let isBranch = 1, isTerminator = 1, noResults = 1 in {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1, noResults = 1 in
def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst",
[/*(ARMbrcond bb:$dst, imm:$cc)*/]>;
//===----------------------------------------------------------------------===//
@ -522,7 +522,7 @@ def tUXTH : TI<(ops GPR:$dst, GPR:$src),
// Expanded by the scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
def tMOVCCr :
PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc),
"@ tMOVCCr $cc",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;

16
lib/Target/ARM/ARMInstrVFP.td
View File

@ -366,22 +366,22 @@ def FNMSCS : ASI<(ops SPR:$dst, SPR:$dstin, SPR:$a, SPR:$b),
// FP Conditional moves.
//
def FCPYDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
"fcpyd$cc $dst, $true",
def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
"fcpyd", " $dst, $true",
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FCPYScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
"fcpys$cc $dst, $true",
def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
"fcpys", " $dst, $true",
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FNEGDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
"fnegd$cc $dst, $true",
def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
"fnegd", " $dst, $true",
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
def FNEGScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
"fnegs$cc $dst, $true",
def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
"fnegs", " $dst, $true",
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;