6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-22 23:24:59 +00:00
Code Issues Projects Releases Wiki Activity

* The itf exposed by InstrScheduling is now a single function to create the right pass

Browse Source 
* InstructionScheduling is now a real pass
* InstrSched _uses_ LiveVar analysis, instead of creating it's own copy many times
  through a loop.  In this was LiveVarAnalysis is actually even SHARED by Register
  allocation.
* SchedPriorities is now passed the live var information in


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-02-04 20:02:16 +00:00
parent 4fd2dbbf1d
commit 9adb7ad457
6 changed files with 126 additions and 102 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@@ -14,6 +14,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
#include "llvm/CodeGen/MachineCodeForMethod.h"
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h" // FIXME: Remove when AnalysisUsage sets can be symbolic!
#include "llvm/Target/TargetMachine.h"
#include "llvm/BasicBlock.h"
#include "SchedPriorities.h"
@@ -1491,46 +1492,60 @@ instrIsFeasible(const SchedulingManager& S,
// are still in SSA form.
//---------------------------------------------------------------------------
bool
ScheduleInstructionsWithSSA(Method* method,
const TargetMachine &target)
{
SchedGraphSet graphSet(method, target);
if (SchedDebugLevel >= Sched_PrintSchedGraphs)
{
cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
graphSet.dump();
namespace {
class InstructionSchedulingWithSSA : public MethodPass {
const TargetMachine &Target;
public:
inline InstructionSchedulingWithSSA(const TargetMachine &T) : Target(T) {}
// getAnalysisUsageInfo - We use LiveVarInfo...
virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
Pass::AnalysisSet &Destroyed,
Pass::AnalysisSet &Provided) {
Requires.push_back(MethodLiveVarInfo::ID);
}
bool runOnMethod(Method *M) {
cerr << "Instr scheduling failed for method " << ((Value*)M)->getName()
<< "\n\n";
SchedGraphSet graphSet(M, Target);
for (SchedGraphSet::const_iterator GI=graphSet.begin();
GI != graphSet.end(); ++GI)
{
SchedGraph* graph = GI->second;
const vector<const BasicBlock*>& bbvec = graph->getBasicBlocks();
assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
const BasicBlock* bb = bbvec[0];
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
graphSet.dump();
}
for (SchedGraphSet::const_iterator GI=graphSet.begin();
GI != graphSet.end(); ++GI) {
SchedGraph* graph = GI->second;
const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
const BasicBlock* bb = bbvec[0];
if (SchedDebugLevel >= Sched_PrintSchedTrace)
cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
if (SchedDebugLevel >= Sched_PrintSchedTrace)
cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
SchedPriorities schedPrio(method, graph); // expensive!
SchedulingManager S(target, graph, schedPrio);
ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
RecordSchedule(GI->first, S); // records schedule in BB
// expensive!
SchedPriorities schedPrio(M, graph, getAnalysis<MethodLiveVarInfo>());
SchedulingManager S(Target, graph, schedPrio);
ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
RecordSchedule(GI->first, S); // records schedule in BB
}
if (SchedDebugLevel >= Sched_PrintMachineCode) {
cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
MachineCodeForMethod::get(M).dump();
}
return false;
}
if (SchedDebugLevel >= Sched_PrintMachineCode)
{
cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
MachineCodeForMethod::get(method).dump();
}
return false; // no reason to fail yet
};
} // end anonymous namespace
MethodPass *createInstructionSchedulingWithSSAPass(const TargetMachine &T) {
return new InstructionSchedulingWithSSA(T);
}