diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 33a068d9962..9dd14618dc0 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -430,7 +430,7 @@ public:
     : SelectionDAGISel(Lowering), Lowering(TM) {
   }
 
-  SDNode *Select(SDOperand &Result, SDOperand Op);
+  SDNode *Select(SDOperand Op);
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
   bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
 
@@ -496,12 +496,12 @@ bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
   return true;      //any address fits in a register
 }
 
-SDNode *ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
 
   switch (N->getOpcode()) {
   default:
-    return SelectCode(Result, Op);
+    return SelectCode(Op);
     break;
   }
   return NULL;
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 2fb8a227658..d84f260446c 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -110,7 +110,7 @@ namespace {
 
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDOperand &Result, SDOperand Op);
+    SDNode *Select(SDOperand Op);
     
     /// InstructionSelectBasicBlock - This callback is invoked by
     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
@@ -145,7 +145,7 @@ namespace {
 private:
     SDOperand getGlobalBaseReg();
     SDOperand getGlobalRetAddr();
-    SDOperand SelectCALL(SDOperand Op);
+    void SelectCALL(SDOperand Op);
 
   };
 }
@@ -182,18 +182,17 @@ void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
       N->getOpcode() < AlphaISD::FIRST_NUMBER) {
-    Result = Op;
     return NULL;   // Already selected.
   }
 
   switch (N->getOpcode()) {
   default: break;
   case AlphaISD::CALL:
-    Result = SelectCALL(Op);
+    SelectCALL(Op);
     return NULL;
 
   case ISD::FrameIndex: {
@@ -202,14 +201,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                 CurDAG->getTargetFrameIndex(FI, MVT::i32),
                                 getI64Imm(0)).Val;
   }
-  case AlphaISD::GlobalBaseReg: 
-    Result = getGlobalBaseReg();
+  case AlphaISD::GlobalBaseReg: {
+    SDOperand Result = getGlobalBaseReg();
     ReplaceUses(Op, Result);
     return NULL;
-  case AlphaISD::GlobalRetAddr:
-    Result = getGlobalRetAddr();
+  }
+  case AlphaISD::GlobalRetAddr: {
+    SDOperand Result = getGlobalRetAddr();
     ReplaceUses(Op, Result);
     return NULL;
+  }
   
   case AlphaISD::DivCall: {
     SDOperand Chain = CurDAG->getEntryNode();
@@ -236,17 +237,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   case ISD::READCYCLECOUNTER: {
     SDOperand Chain = N->getOperand(0);
     AddToISelQueue(Chain); //Select chain
-    Result = SDOperand(CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
-                                             Chain), Op.ResNo);
-    return Result.Val;
+    return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
+                                 Chain);
   }
 
   case ISD::Constant: {
     uint64_t uval = cast<ConstantSDNode>(N)->getValue();
     
     if (uval == 0) {
-      Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
-                                      MVT::i64);
+      SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
+                                                Alpha::R31, MVT::i64);
       ReplaceUses(Op, Result);
       return NULL;
     }
@@ -329,10 +329,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                              CurDAG->getRegister(Alpha::R31, MVT::i64),
                                              ST), 0);
       }
-      Result = SDOperand(CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
-                                               CurDAG->getRegister(Alpha::R31, MVT::i64),
-                                               LD), 0);
-      return Result.Val;
+      return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, 
+                                   CurDAG->getRegister(Alpha::R31, MVT::i64),
+                                   LD);
     }
     break;
 
@@ -366,9 +365,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                              CurDAG->getRegister(Alpha::R31, MVT::i64),
                                              ST), 0);
       }
-      Result = SDOperand(CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
-                                               MVT::f64, FV, TV, LD), 0);
-      return Result.Val;
+      return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
+                                   MVT::f64, FV, TV, LD);
     }
     break;
 
@@ -397,9 +395,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 	    SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
                                             N->getOperand(0).getOperand(0),
 					    getI64Imm(get_zapImm(mask))), 0);
-	  Result = SDOperand(CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, 
-						   getI64Imm(sval)), 0);
-	  return Result.Val;
+	  return CurDAG->getTargetNode(Alpha::SRL, MVT::i64, Z, 
+                                       getI64Imm(sval));
 	}
       }
     break;
@@ -407,10 +404,10 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 
   }
 
-  return SelectCode(Result, Op);
+  return SelectCode(Op);
 }
 
-SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
+void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
   //TODO: add flag stuff to prevent nondeturministic breakage!
 
   SDNode *N = Op.Val;
@@ -500,7 +497,6 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
    CallResults.push_back(Chain);
    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
      ReplaceUses(Op.getValue(i), CallResults[i]);
-   return CallResults[Op.ResNo];
 }
 
 
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index f61c9e1e535..b384705e512 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -65,7 +65,7 @@ namespace {
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDOperand &Result, SDOperand N);
+    SDNode *Select(SDOperand N);
     
     SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
                                    unsigned OCHi, unsigned OCLo,
@@ -94,7 +94,7 @@ namespace {
 #include "IA64GenDAGISel.inc"
     
 private:
-    SDOperand SelectDIV(SDOperand Op);
+    SDNode *SelectDIV(SDOperand Op);
   };
 }
 
@@ -111,7 +111,7 @@ void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
   ScheduleAndEmitDAG(DAG);
 }
 
-SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
+SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
   SDNode *N = Op.Val;
   SDOperand Chain = N->getOperand(0);
   SDOperand Tmp1 = N->getOperand(0);
@@ -245,7 +245,7 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
       Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
                                      TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
       Chain = SDOperand(Result, 1);
-      return SDOperand(Result, 0); // XXX: early exit!
+      return Result; // XXX: early exit!
     } else { // this is *not* an FP divide, so there's a bit left to do:
     
       SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
@@ -292,19 +292,17 @@ SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
         Chain = SDOperand(Result, 1);
       }
 
-      return SDOperand(Result, 0);
+      return Result;
     } // wasn't an FP divide
 }
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
-      N->getOpcode() < IA64ISD::FIRST_NUMBER) {
-    Result = Op;
+      N->getOpcode() < IA64ISD::FIRST_NUMBER)
     return NULL;   // Already selected.
-  }
 
   switch (N->getOpcode()) {
   default: break;
@@ -379,15 +377,13 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
 
    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
      ReplaceUses(Op.getValue(i), CallResults[i]);
-   Result = CallResults[Op.ResNo];
    return NULL;
   }
   
   case IA64ISD::GETFD: {
     SDOperand Input = N->getOperand(0);
     AddToISelQueue(Input);
-    Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
-    return Result.Val;
+    return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
   } 
   
   case ISD::FDIV:
@@ -395,8 +391,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   case ISD::UDIV:
   case ISD::SREM:
   case ISD::UREM:
-    Result = SelectDIV(Op);
-    return Result.Val;
+    return SelectDIV(Op);
  
   case ISD::TargetConstantFP: {
     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
@@ -425,9 +420,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     Constant *C = CP->get();
     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
                                                   CP->getAlignment());
-    Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
-	                      CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
-    return Result.Val;
+    return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
+                                 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
   }
 
   case ISD::GlobalAddress: {
@@ -435,8 +429,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
     SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
     SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, 
 	                          CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
-    Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
-    return Result.Val;
+    return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
   }
   
 /* XXX  case ISD::ExternalSymbol: {
@@ -564,7 +557,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
                                 N->getOperand(1), N0).Val;
   }
   
-  return SelectCode(Result, Op);
+  return SelectCode(Op);
 }
 
 
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 40f10057d57..22752abed09 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -79,11 +79,11 @@ namespace {
     
     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
     /// base register.  Return the virtual register that holds this value.
-    SDOperand getGlobalBaseReg();
+    SDNode *getGlobalBaseReg();
     
     // Select - Convert the specified operand from a target-independent to a
     // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDOperand &Result, SDOperand Op);
+    SDNode *Select(SDOperand Op);
     
     SDNode *SelectBitfieldInsert(SDNode *N);
 
@@ -252,7 +252,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
 /// getGlobalBaseReg - Output the instructions required to put the
 /// base address to use for accessing globals into a register.
 ///
-SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
+SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
   if (!GlobalBaseReg) {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
@@ -267,7 +267,7 @@ SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
     BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
     BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
   }
-  return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy());
+  return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
 }
 
 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
@@ -902,20 +902,18 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
 
 // Select - Convert the specified operand from a target-independent to a
 // target-specific node if it hasn't already been changed.
-SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
-      N->getOpcode() < PPCISD::FIRST_NUMBER) {
-    Result = Op;
+      N->getOpcode() < PPCISD::FIRST_NUMBER)
     return NULL;   // Already selected.
-  }
 
   switch (N->getOpcode()) {
   default: break;
   case ISD::SETCC:
     return SelectSETCC(Op);
   case PPCISD::GlobalBaseReg:
-    return getGlobalBaseReg().Val;
+    return getGlobalBaseReg();
     
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
@@ -1118,7 +1116,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   case PPCISD::CALL:             return MySelect_PPCcall(Op);
   }
   
-  return SelectCode(Result, Op);
+  return SelectCode(Op);
 }
 
 
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index cb5ff8ba166..7c298c78e5a 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -966,7 +966,7 @@ public:
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
-  SDNode *Select(SDOperand &Result, SDOperand Op);
+  SDNode *Select(SDOperand Op);
 
   // Complex Pattern Selectors.
   bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
@@ -1063,13 +1063,11 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
   return true;
 }
 
-SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
   SDNode *N = Op.Val;
   if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
-      N->getOpcode() < SPISD::FIRST_NUMBER) {
-    Result = Op;
+      N->getOpcode() < SPISD::FIRST_NUMBER)
     return NULL;   // Already selected.
-  }
 
   switch (N->getOpcode()) {
   default: break;
@@ -1113,7 +1111,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   }
   }
   
-  return SelectCode(Result, Op);
+  return SelectCode(Op);
 }
 
 
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index abe76271a95..6ec294c3f3a 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -123,7 +123,7 @@ namespace {
 #include "X86GenDAGISel.inc"
 
   private:
-    SDNode *Select(SDOperand &Result, SDOperand N);
+    SDNode *Select(SDOperand N);
 
     bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
     bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
@@ -176,7 +176,7 @@ namespace {
 
     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
     /// base register.  Return the virtual register that holds this value.
-    SDOperand getGlobalBaseReg();
+    SDNode *getGlobalBaseReg();
 
 #ifndef NDEBUG
     unsigned Indent;
@@ -582,7 +582,7 @@ static bool isRegister0(SDOperand Op) {
 /// getGlobalBaseReg - Output the instructions required to put the
 /// base address to use for accessing globals into a register.
 ///
-SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
+SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
   if (!GlobalBaseReg) {
     // Insert the set of GlobalBaseReg into the first MBB of the function
     MachineBasicBlock &FirstMBB = BB->getParent()->front();
@@ -594,7 +594,7 @@ SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
     BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
     BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
   }
-  return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
+  return CurDAG->getRegister(GlobalBaseReg, MVT::i32).Val;
 }
 
 static SDNode *FindCallStartFromCall(SDNode *Node) {
@@ -604,7 +604,7 @@ static SDNode *FindCallStartFromCall(SDNode *Node) {
   return FindCallStartFromCall(Node->getOperand(0).Val);
 }
 
-SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
+SDNode *X86DAGToDAGISel::Select(SDOperand N) {
   SDNode *Node = N.Val;
   MVT::ValueType NVT = Node->getValueType(0);
   unsigned Opc, MOpc;
@@ -619,7 +619,6 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
 #endif
 
   if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
-    Result = N;
 #ifndef NDEBUG
     DEBUG(std::cerr << std::string(Indent-2, ' '));
     DEBUG(std::cerr << "== ");
@@ -633,8 +632,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
   switch (Opcode) {
     default: break;
     case X86ISD::GlobalBaseReg: 
-      Result = getGlobalBaseReg();
-      return Result.Val;
+      return getGlobalBaseReg();
 
     case ISD::ADD: {
       // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
@@ -736,7 +734,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
           SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
       }
 
-      Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
+      SDOperand Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
       ReplaceUses(N.getValue(0), Result);
       if (foldedLoad)
         ReplaceUses(N1.getValue(1), Result.getValue(1));
@@ -840,8 +838,8 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
           SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
       }
 
-      Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
-                                      NVT, InFlag);
+      SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
+                                                NVT, InFlag);
       ReplaceUses(N.getValue(0), Result);
       if (foldedLoad)
         ReplaceUses(N1.getValue(1), Result.getValue(1));
@@ -878,28 +876,31 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
         AddToISelQueue(Node->getOperand(0));
         SDOperand Tmp =
           SDOperand(CurDAG->getTargetNode(Opc, VT, Node->getOperand(0)), 0);
-        Result = SDOperand(CurDAG->getTargetNode(Opc2, NVT, Tmp), 0);
+        SDNode *ResNode = CurDAG->getTargetNode(Opc2, NVT, Tmp);
       
 #ifndef NDEBUG
         DEBUG(std::cerr << std::string(Indent-2, ' '));
         DEBUG(std::cerr << "=> ");
-        DEBUG(Result.Val->dump(CurDAG));
+        DEBUG(ResNode->dump(CurDAG));
         DEBUG(std::cerr << "\n");
         Indent -= 2;
 #endif
-        return Result.Val;
+        return ResNode;
       }
 
       break;
     }
   }
 
-  SDNode *ResNode = SelectCode(Result, N);
+  SDNode *ResNode = SelectCode(N);
 
 #ifndef NDEBUG
   DEBUG(std::cerr << std::string(Indent-2, ' '));
   DEBUG(std::cerr << "=> ");
-  DEBUG(Result.Val->dump(CurDAG));
+  if (ResNode == NULL || ResNode == N.Val)
+    DEBUG(N.Val->dump(CurDAG));
+  else
+    DEBUG(ResNode->dump(CurDAG));
   DEBUG(std::cerr << "\n");
   Indent -= 2;
 #endif
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index 867e19e21b5..58a4f5aa48c 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -2517,7 +2517,6 @@ public:
           emitCode("AddToISelQueue(" + Val + ");");
           if (isRoot && N->isLeaf()) {
             emitCode("ReplaceUses(N, " + Val + ");");
-            emitCode("Result = " + Val + ";");
             emitCode("return NULL;");
           }
         }
@@ -2768,43 +2767,26 @@ public:
 
         // User does not expect the instruction would produce a chain!
         if ((!InputHasChain && NodeHasChain) && NodeHasOutFlag) {
-          if (PatResults == 0) {
-            emitCode("Result = SDOperand(ResNode, N.ResNo+1);");
-          } else {
-	    assert(PatResults == 1);
-            emitCode("Result = (N.ResNo == 0) ? SDOperand(ResNode, 0) :"
-		     " SDOperand(ResNode, 1);");
-          }
+          ;
         } else if (InputHasChain && !NodeHasChain) {
           // One of the inner node produces a chain.
-          if (NodeHasOutFlag) {
-            emitCode("Result = (N.ResNo < " + utostr(PatResults) +
-		     ") ? SDOperand(ResNode, N.ResNo) : " +
-		     "(N.ResNo > " + utostr(PatResults) + ") ? " +
-		     "SDOperand(ResNode, N.ResNo-1) : " + ChainName + "));");
+          if (NodeHasOutFlag)
 	    emitCode("ReplaceUses(SDOperand(N.Val, " + utostr(PatResults+1) +
 		     "), SDOperand(ResNode, N.ResNo-1));");
-	  } else {
-            emitCode("Result = (N.ResNo < " + utostr(PatResults) +
-		     ") ? SDOperand(ResNode, N.ResNo) : " +
-		     ChainName + ";");
-	  }
 	  for (unsigned i = 0; i < PatResults; ++i)
 	    emitCode("ReplaceUses(SDOperand(N.Val, " + utostr(i) +
 		     "), SDOperand(ResNode, " + utostr(i) + "));");
 	  emitCode("ReplaceUses(SDOperand(N.Val, " + utostr(PatResults) +
 		   "), " + ChainName + ");");
 	  RetSelected = false;
-	} else {
-          emitCode("Result = SDOperand(ResNode, N.ResNo);");
         }
 
 	if (RetSelected)
-	  emitCode("return Result.Val;");
+	  emitCode("return ResNode;");
 	else
 	  emitCode("return NULL;");
       } else {
-        std::string Code = "Result = CurDAG->SelectNodeTo(N.Val, Opc" +
+        std::string Code = "return CurDAG->SelectNodeTo(N.Val, Opc" +
           utostr(OpcNo);
         if (N->getTypeNum(0) != MVT::isVoid)
           Code += ", VT" + utostr(VTNo);
@@ -2814,8 +2796,7 @@ public:
           Code += ", " + AllOps[i];
         if (NodeHasInFlag || HasImpInputs)
           Code += ", InFlag";
-        emitCode(Code + ");");
-        emitCode("return Result.Val;");
+        emitCode(Code + ").Val;");
         emitOpcode(II.Namespace + "::" + II.TheDef->getName());
         if (N->getTypeNum(0) != MVT::isVoid)
           emitVT(getEnumName(N->getTypeNum(0)));
@@ -2833,10 +2814,8 @@ public:
       emitCode("SDOperand Tmp" + utostr(ResNo) + " = Transform_" + Op->getName()
                + "(" + Ops.back() + ".Val);");
       NodeOps.push_back("Tmp" + utostr(ResNo));
-      if (isRoot) {
-        emitCode("Result = Tmp" + utostr(ResNo) + ";");
-        emitCode("return Result.Val;");
-      }
+      if (isRoot)
+        emitCode("return Tmp" + utostr(ResNo) + ".Val;");
       return NodeOps;
     } else {
       N->dump();
@@ -3328,8 +3307,8 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
             AddedInits.push_back(GeneratedCode[j].second);
         }
 
-        std::string CalleeCode = "(SDOperand &Result, const SDOperand &N";
-        std::string CallerCode = "(Result, N";
+        std::string CalleeCode = "(const SDOperand &N";
+        std::string CallerCode = "(N";
         for (unsigned j = 0, e = TargetOpcodes.size(); j != e; ++j) {
           CalleeCode += ", unsigned Opc" + utostr(j);
           CallerCode += ", " + TargetOpcodes[j];
@@ -3392,7 +3371,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
         OpVTI->second.push_back(OpVTStr);
 
       OS << "SDNode *Select_" << OpName << (OpVTStr != "" ? "_" : "")
-         << OpVTStr << "(SDOperand &Result, const SDOperand &N) {\n";    
+         << OpVTStr << "(const SDOperand &N) {\n";    
 
       // Loop through and reverse all of the CodeList vectors, as we will be
       // accessing them from their logical front, but accessing the end of a
@@ -3431,7 +3410,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
   }
   
   // Emit boilerplate.
-  OS << "SDNode *Select_INLINEASM(SDOperand& Result, SDOperand N) {\n"
+  OS << "SDNode *Select_INLINEASM(SDOperand N) {\n"
      << "  std::vector<SDOperand> Ops(N.Val->op_begin(), N.Val->op_end());\n"
      << "  AddToISelQueue(N.getOperand(0)); // Select the chain.\n\n"
      << "  // Select the flag operand.\n"
@@ -3443,16 +3422,14 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
      << "  VTs.push_back(MVT::Flag);\n"
      << "  SDOperand New = CurDAG->getNode(ISD::INLINEASM, VTs, &Ops[0], "
                  "Ops.size());\n"
-     << "  Result = New.getValue(N.ResNo);\n"
-     << "  return Result.Val;\n"
+     << "  return New.Val;\n"
      << "}\n\n";
   
   OS << "// The main instruction selector code.\n"
-     << "SDNode *SelectCode(SDOperand &Result, SDOperand N) {\n"
+     << "SDNode *SelectCode(SDOperand N) {\n"
      << "  if (N.getOpcode() >= ISD::BUILTIN_OP_END &&\n"
      << "      N.getOpcode() < (ISD::BUILTIN_OP_END+" << InstNS
      << "INSTRUCTION_LIST_END)) {\n"
-     << "    Result = N;\n"
      << "    return NULL;   // Already selected.\n"
      << "  }\n\n"
      << "  switch (N.getOpcode()) {\n"
@@ -3466,7 +3443,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
      << "  case ISD::TargetFrameIndex:\n"
      << "  case ISD::TargetJumpTable:\n"
      << "  case ISD::TargetGlobalAddress: {\n"
-     << "    Result = N;\n"
      << "    return NULL;\n"
      << "  }\n"
      << "  case ISD::AssertSext:\n"
@@ -3480,10 +3456,9 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
      << "  case ISD::CopyToReg: {\n"
      << "    for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)\n"
      << "      AddToISelQueue(N.getOperand(i));\n"
-     << "    Result = N;\n"
      << "    return NULL;\n"
      << "  }\n"
-     << "  case ISD::INLINEASM:  return Select_INLINEASM(Result, N);\n";
+     << "  case ISD::INLINEASM:  return Select_INLINEASM(N);\n";
 
     
   // Loop over all of the case statements, emiting a call to each method we
@@ -3503,7 +3478,7 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
     if (OpVTs.size() == 1) {
       std::string &VTStr = OpVTs[0];
       OS << "    return Select_" << OpName
-         << (VTStr != "" ? "_" : "") << VTStr << "(Result, N);\n";
+         << (VTStr != "" ? "_" : "") << VTStr << "(N);\n";
     } else {
       if (OpcodeInfo.getNumResults())
         OS << "    MVT::ValueType NVT = N.Val->getValueType(0);\n";
@@ -3523,11 +3498,11 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) {
         }
         OS << "    case MVT::" << VTStr << ":\n"
            << "      return Select_" << OpName
-           << "_" << VTStr << "(Result, N);\n";
+           << "_" << VTStr << "(N);\n";
       }
       OS << "    default:\n";
       if (Default != -1)
-        OS << "      return Select_" << OpName << "(Result, N);\n";
+        OS << "      return Select_" << OpName << "(N);\n";
       else
 	OS << "      break;\n";
       OS << "    }\n";
@@ -3647,12 +3622,11 @@ OS << "  unsigned NumKilled = ISelKilled.size();\n";
      << "  HandleSDNode Dummy(CurDAG->getRoot());\n"
      << "  ISelQueue.push_back(CurDAG->getRoot().Val);\n";
   OS << "  while (!ISelQueue.empty()) {\n";
-  OS << "    SDOperand Tmp;\n";
   OS << "    SDNode *Node = ISelQueue.front();\n";
   OS << "    std::pop_heap(ISelQueue.begin(), ISelQueue.end(), isel_sort());\n";
   OS << "    ISelQueue.pop_back();\n";
   OS << "    if (!isSelected(Node->getNodeId())) {\n";
-  OS << "      SDNode *ResNode = Select(Tmp, SDOperand(Node, 0));\n";
+  OS << "      SDNode *ResNode = Select(SDOperand(Node, 0));\n";
   OS << "      if (ResNode && ResNode != Node) ReplaceUses(Node, ResNode);\n";
   OS << "    }\n";
   OS << "  }\n";