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Update tests to use sse4.2 instead of sse42.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2013-08-23 20:46:35 +00:00
parent 7cb1b5f5bf
commit 9b14371830
23 changed files with 24 additions and 24 deletions
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2
test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=x86-64 -mattr=-sse42,+sse4.1 < %s | FileCheck %s
; RUN: llc -march=x86-64 -mattr=-sse4.2,+sse4.1 < %s | FileCheck %s
; Make sure we don't load from the location pointed to by %p
; twice: it has non-obvious performance implications, and
; the relevant transformation doesn't know how to update

2
test/CodeGen/X86/bc-extract.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
define float @extractFloat1() nounwind {

2
test/CodeGen/X86/mmx-punpckhdq.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=x86_64-apple-darwin10 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=x86_64-apple-darwin10 | FileCheck %s
; There are no MMX operations in bork; promoted to XMM.
define void @bork(<1 x i64>* %x) {

2
test/CodeGen/X86/scalar_widen_div.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
; Verify when widening a divide/remainder operation, we only generate a
; divide/rem per element since divide/remainder can trap.

4
test/CodeGen/X86/sse42.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X64
declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind

2
test/CodeGen/X86/sse42_64.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X64
declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind

2
test/CodeGen/X86/vec_compare-sse4.ll
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@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
; RUN: llc < %s -march=x86 -mattr=-sse4.2,+sse4.1 | FileCheck %s -check-prefix=SSE41
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s -check-prefix=SSE42
define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
; SSE42-LABEL: test1:

2
test/CodeGen/X86/vec_insert-7.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=i686-apple-darwin9 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=i686-apple-darwin9 | FileCheck %s
; MMX insertelement is not available; these are promoted to XMM.
; (Without SSE they are split to two ints, and the code is much better.)

2
test/CodeGen/X86/widen_arith-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse4.2 | FileCheck %s
define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind {
entry:

2
test/CodeGen/X86/widen_arith-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: padd
; CHECK: pand

2
test/CodeGen/X86/widen_arith-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
; CHECK: psubw
; CHECK-NEXT: pmullw

2
test/CodeGen/X86/widen_arith-5.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
; CHECK: movdqa
; CHECK: pslld $2
; CHECK: psubd

2
test/CodeGen/X86/widen_arith-6.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: mulps
; CHECK: addps

2
test/CodeGen/X86/widen_cast-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
; CHECK: pextrd
; CHECK: pextrd
; CHECK: movd

2
test/CodeGen/X86/widen_cast-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: paddd
; CHECK: pextrd
; CHECK: pextrd

2
test/CodeGen/X86/widen_cast-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: psraw
; CHECK: psraw

2
test/CodeGen/X86/widen_cast-5.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: movl
; CHECK: movlpd

2
test/CodeGen/X86/widen_conv-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: paddq
; truncate v2i64 to v2i32

2
test/CodeGen/X86/widen_conv-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: cwtl
; CHECK: cwtl

2
test/CodeGen/X86/widen_conv-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; CHECK: cvtsi2ss
; sign to float v2i16 to v2f32

2
test/CodeGen/X86/widen_conv-4.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
; CHECK-NOT: cvtsi2ss
; unsigned to float v7i16 to v7f32

2
test/CodeGen/X86/widen_extract-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86-64 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
; widen extract subvector
define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {

2
test/CodeGen/X86/widen_shuffle-1.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
; widening shuffle v3float and then a add
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {