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Tidy up spacing in some tablegen outputs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-04-03 06:52:47 +00:00
parent 769bbfd951
commit 9b1b25f063
2 changed files with 9 additions and 11 deletions
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4
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -477,7 +477,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
static void static void
emitRegisterNameString(raw_ostream &O, StringRef AltName, emitRegisterNameString(raw_ostream &O, StringRef AltName,
const std::vector<CodeGenRegister*> &Registers) { const std::vector<CodeGenRegister*> &Registers) {
SequenceToOffsetTable<std::string> StringTable; SequenceToOffsetTable<std::string> StringTable;
SmallVector<std::string, 4> AsmNames(Registers.size()); SmallVector<std::string, 4> AsmNames(Registers.size());
for (unsigned i = 0, e = Registers.size(); i != e; ++i) { for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
@ -525,7 +525,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
O << "\n "; O << "\n ";
O << StringTable.get(AsmNames[i]) << ", "; O << StringTable.get(AsmNames[i]) << ", ";
} }
O << " };\n" O << "\n };\n"
<< "\n"; << "\n";
} }

16
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -578,8 +578,7 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
const std::string &TargetName = Target.getName(); const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo"; std::string ClassName = TargetName + "GenRegisterInfo";
OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
OS << "#include <string>\n\n";
OS << "namespace llvm {\n\n"; OS << "namespace llvm {\n\n";
@ -812,19 +811,18 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit extra information about registers. // Emit extra information about registers.
const std::string &TargetName = Target.getName(); const std::string &TargetName = Target.getName();
OS << "\n static const TargetRegisterInfoDesc " OS << "\nstatic const TargetRegisterInfoDesc "
<< TargetName << "RegInfoDesc[] = " << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
<< "{ // Extra Descriptors\n"; OS << " { 0, 0 },\n";
OS << " { 0, 0 },\n";
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = *Regs[i]; const CodeGenRegister &Reg = *Regs[i];
OS << " { "; OS << " { ";
OS << Reg.CostPerUse << ", " OS << Reg.CostPerUse << ", "
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
} }
OS << " };\n"; // End of register descriptors... OS << "};\n"; // End of register descriptors...
// Calculate the mapping of subregister+index pairs to physical registers. // Calculate the mapping of subregister+index pairs to physical registers.
@ -833,7 +831,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Emit SubRegIndex names, skipping 0 // Emit SubRegIndex names, skipping 0
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
OS << "\n static const char *const " << TargetName OS << "\nstatic const char *const " << TargetName
<< "SubRegIndexTable[] = { \""; << "SubRegIndexTable[] = { \"";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
OS << SubRegIndices[i]->getName(); OS << SubRegIndices[i]->getName();