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https://github.com/c64scene-ar/llvm-6502.git
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Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
parent
a3458380b9
commit
9b709f8b3f
@ -92,6 +92,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@ -192,6 +195,13 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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Inst.addOperand(MCOperand::CreateImm(Val));
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Inst.addOperand(MCOperand::CreateImm(0));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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@ -85,12 +85,26 @@ class _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr,
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let DecoderMethod = "DecodeL2RUSBitpInstruction";
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}
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class _FRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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bits<4> a;
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bits<6> b;
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let Inst{15-10} = opc;
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let Inst{9-6} = a;
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let Inst{5-0} = b;
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}
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class _FLRU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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bits<4> a;
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bits<16> b;
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let Inst{31-26} = opc;
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let Inst{25-22} = a;
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let Inst{21-16} = b{5-0};
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let Inst{15-10} = 0b111100;
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let Inst{9-0} = b{15-6};
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}
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class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -182,6 +182,7 @@ def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
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// Address operands
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def MEMii : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let DecoderMethod = "DecodeMEMiiOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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@ -265,26 +266,25 @@ class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
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// Register - U6
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// Operand register - U6
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multiclass FRU6_LRU6_branch<string OpcStr> {
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def _ru6: _FRU6<
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(outs), (ins GRRegs:$cond, brtarget:$dest),
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!strconcat(OpcStr, " $cond, $dest"),
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[]>;
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def _lru6: _FLRU6<
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(outs), (ins GRRegs:$cond, brtarget:$dest),
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!strconcat(OpcStr, " $cond, $dest"),
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[]>;
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multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
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def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
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!strconcat(OpcStr, " $a, $b"), []>;
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def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
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!strconcat(OpcStr, " $a, $b"), []>;
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}
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multiclass FRU6_LRU6_cp<string OpcStr> {
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def _ru6: _FRU6<
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(outs GRRegs:$dst), (ins i32imm:$a),
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!strconcat(OpcStr, " $dst, cp[$a]"),
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[]>;
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def _lru6: _FLRU6<
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(outs GRRegs:$dst), (ins i32imm:$a),
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!strconcat(OpcStr, " $dst, cp[$a]"),
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[]>;
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multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
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def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
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!strconcat(OpcStr, " $a, -$b"), []>;
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def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
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!strconcat(OpcStr, " $a, -$b"), []>;
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}
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multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
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def _ru6: _FRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
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!strconcat(OpcStr, " $a, cp[$b]"), []>;
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def _lru6: _FLRU6<opc, (outs GRRegs:$a), (ins i32imm:$b),
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!strconcat(OpcStr, " $a, cp[$b]"), []>;
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}
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// U6
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@ -537,113 +537,92 @@ def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
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//let Uses = [DP] in ...
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let neverHasSideEffects = 1, isReMaterializable = 1 in
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def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
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"ldaw $dst, dp[$a]",
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[]>;
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def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
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"ldaw $a, dp[$b]", []>;
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let isReMaterializable = 1 in
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def LDAWDP_lru6: _FLRU6<
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(outs GRRegs:$dst), (ins MEMii:$a),
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"ldaw $dst, dp[$a]",
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[(set GRRegs:$dst, ADDRdpii:$a)]>;
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def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b),
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"ldaw $a, dp[$b]",
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[(set GRRegs:$a, ADDRdpii:$b)]>;
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let mayLoad=1 in
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def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a),
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"ldw $dst, dp[$a]",
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[]>;
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def LDWDP_lru6: _FLRU6<
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(outs GRRegs:$dst), (ins MEMii:$a),
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"ldw $dst, dp[$a]",
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[(set GRRegs:$dst, (load ADDRdpii:$a))]>;
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def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
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"ldw $a, dp[$b]", []>;
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def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b),
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"ldw $a, dp[$b]",
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[(set GRRegs:$a, (load ADDRdpii:$b))]>;
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let mayStore=1 in
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def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
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"stw $val, dp[$addr]",
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[]>;
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def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
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"stw $a, dp[$b]", []>;
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def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr),
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"stw $val, dp[$addr]",
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[(store GRRegs:$val, ADDRdpii:$addr)]>;
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def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b),
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"stw $a, dp[$b]",
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[(store GRRegs:$a, ADDRdpii:$b)]>;
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//let Uses = [CP] in ..
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let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
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defm LDWCP : FRU6_LRU6_cp<"ldw">;
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defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
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let Uses = [SP] in {
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let mayStore=1 in {
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def STWSP_ru6 : _FRU6<
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(outs), (ins GRRegs:$val, i32imm:$index),
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"stw $val, sp[$index]",
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[(XCoreStwsp GRRegs:$val, immU6:$index)]>;
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def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
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"stw $a, sp[$b]",
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[(XCoreStwsp GRRegs:$a, immU6:$b)]>;
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def STWSP_lru6 : _FLRU6<
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(outs), (ins GRRegs:$val, i32imm:$index),
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"stw $val, sp[$index]",
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[(XCoreStwsp GRRegs:$val, immU16:$index)]>;
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def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b),
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"stw $a, sp[$b]",
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[(XCoreStwsp GRRegs:$a, immU16:$b)]>;
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}
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let mayLoad=1 in {
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def LDWSP_ru6 : _FRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldw $dst, sp[$b]",
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[]>;
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def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
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"ldw $a, sp[$b]", []>;
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def LDWSP_lru6 : _FLRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldw $dst, sp[$b]",
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[]>;
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def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b),
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"ldw $a, sp[$b]", []>;
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}
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let neverHasSideEffects = 1 in {
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def LDAWSP_ru6 : _FRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[]>;
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def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
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"ldaw $a, sp[$b]", []>;
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def LDAWSP_lru6 : _FLRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[]>;
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def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b),
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"ldaw $a, sp[$b]", []>;
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def LDAWSP_ru6_RRegs : _FRU6<
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(outs RRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[]>;
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let isCodeGenOnly = 1 in
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def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
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"ldaw $a, sp[$b]", []>;
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def LDAWSP_lru6_RRegs : _FLRU6<
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(outs RRegs:$dst), (ins i32imm:$b),
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"ldaw $dst, sp[$b]",
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[]>;
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let isCodeGenOnly = 1 in
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def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
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"ldaw $a, sp[$b]", []>;
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}
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}
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let isReMaterializable = 1 in {
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def LDC_ru6 : _FRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldc $dst, $b",
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[(set GRRegs:$dst, immU6:$b)]>;
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def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
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"ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>;
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def LDC_lru6 : _FLRU6<
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(outs GRRegs:$dst), (ins i32imm:$b),
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"ldc $dst, $b",
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[(set GRRegs:$dst, immU16:$b)]>;
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def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b),
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"ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>;
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}
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def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val),
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"setc res[$r], $val",
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[(int_xcore_setc GRRegs:$r, immU6:$val)]>;
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def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
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"setc res[$a], $b",
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[(int_xcore_setc GRRegs:$a, immU6:$b)]>;
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def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val),
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"setc res[$r], $val",
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[(int_xcore_setc GRRegs:$r, immU16:$val)]>;
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def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
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"setc res[$a], $b",
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[(int_xcore_setc GRRegs:$a, immU16:$b)]>;
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// Operand register - U6
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let isBranch = 1, isTerminator = 1 in {
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defm BRFT: FRU6_LRU6_branch<"bt">;
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defm BRBT: FRU6_LRU6_branch<"bt">;
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defm BRFF: FRU6_LRU6_branch<"bf">;
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defm BRBF: FRU6_LRU6_branch<"bf">;
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defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
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defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
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defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
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defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
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}
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// U6
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@ -312,3 +312,83 @@
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# CHECK: ldaw r8, r2[-9]
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0x09 0xfd 0xec 0xa7
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# ru6 / lru6 instructions
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# CHECK: bt r6, -5
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0x85 0x75
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# CHECK: bt r10, -451
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0x07 0xf0 0x83 0x76
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# CHECK: bt r8, 10
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0x0a 0x72
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# CHECK: bt r1, 6451
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0x64 0xf0 0x73 0x70
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# CHECK: bf r5, 8
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0x48 0x79
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# CHECK: bf r6, 65
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0x01 0xf0 0x81 0x79
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# CHECK: bf r1, 53
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0x75 0x78
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# CHECK: bf r10, 101
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0x01 0xf0 0xa5 0x7a
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# CHECK: ldaw r11, dp[63]
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0xff 0x62
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# CHECK: ldaw r1, dp[456]
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0x07 0xf0 0x48 0x60
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# CHECK: ldaw r3, sp[2]
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0xc2 0x64
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# CHECK: ldaw r8, sp[65535]
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0xff 0xf3 0x3f 0x66
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# CHECK: ldc r3, 30
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0xde 0x68
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# CHECK: ldc r11, 1000
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0x0f 0xf0 0xe8 0x6a
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# CHECK: ldw r0, cp[4]
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0x04 0x6c
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# CHECK: ldw r1, cp[32345]
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0xf9 0xf1 0x59 0x6c
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# CHECK: ldw r10, dp[16]
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0x90 0x5a
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# CHECK: ldw r10, dp[76]
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0x01 0xf0 0x8c 0x5a
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# CHECK: ldw r8, sp[51]
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0x33 0x5e
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# CHECK: ldw r8, sp[1225]
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0x13 0xf0 0x09 0x5e
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# CHECK: setc res[r5], 36
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0x64 0xe9
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# CHECK: setc res[r2], 40312
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0x75 0xf2 0xb8 0xe8
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# CHECK: stw r8, dp[14]
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0x0e 0x52
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# CHECK: stw r9, dp[654]
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0x0a 0xf0 0x4e 0x52
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# CHECK: stw r1, sp[32]
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0x60 0x54
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# CHECK: stw r0, sp[8761]
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0x88 0xf0 0x39 0x54
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