6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-05 12:31:33 +00:00
Code Issues Projects Releases Wiki Activity

Override TRI::getSubClassWithSubReg for X86.

Browse Source 
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-10-05 20:26:33 +00:00
parent 11f1a8335e
commit 9bb272c900
2 changed files with 15 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -111,6 +111,18 @@ X86RegisterInfo::getSEHRegNum(unsigned i) const {
return reg;
}
const TargetRegisterClass *
X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
unsigned Idx) const {
// The sub_8bit sub-register index is more constrained in 32-bit mode.
// It behaves just like the sub_8bit_hi index.
if (!Is64Bit && Idx == X86::sub_8bit)
Idx = X86::sub_8bit_hi;
// Forward to TableGen's default version.
return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
}
const TargetRegisterClass *
X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B,

3
lib/Target/X86/X86RegisterInfo.h
View File

@ -74,6 +74,9 @@ public:
getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B, unsigned Idx) const;
virtual const TargetRegisterClass *
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;