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https://github.com/c64scene-ar/llvm-6502.git
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[PowerPC] Add handling for conversions to fast-isel.
Yet another chunk of fast-isel code. This one handles various conversions involving floating-point. (It also includes some miscellaneous handling throughout the back end for LWA_32 and LWAX_32 that should have been part of the load-store patch.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189677 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
2cc396bfb0
commit
9bc94276e7
@ -19,6 +19,7 @@
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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#include "PPCGenAsmWriter.inc"
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@ -78,6 +79,17 @@ void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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}
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}
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// For fast-isel, a COPY_TO_REGCLASS may survive this long. This is
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// used when converting a 32-bit float to a 64-bit float as part of
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// conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
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// as otherwise we have problems with incorrect register classes
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// in machine instruction verification. For now, just avoid trying
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// to print it as such an instruction has no effect (a 32-bit float
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// in a register is already in 64-bit form, just with lower
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// precision). FIXME: Is there a better solution?
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if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
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return;
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printInstruction(MI, O);
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printAnnotation(O, Annot);
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}
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@ -704,6 +704,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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break;
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case PPC::LD:
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case PPC::STD:
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case PPC::LWA_32:
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case PPC::LWA: {
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// Verify alignment is legal, so we don't create relocations
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// that can't be supported.
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@ -109,6 +109,10 @@ class PPCFastISel : public FastISel {
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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bool SelectCmp(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectIToFP(const Instruction *I, bool IsSigned);
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bool SelectFPToI(const Instruction *I, bool IsSigned);
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bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
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bool SelectRet(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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@ -135,6 +139,9 @@ class PPCFastISel : public FastISel {
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const TargetRegisterClass *RC);
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unsigned PPCMaterialize64BitInt(int64_t Imm,
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const TargetRegisterClass *RC);
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unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
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unsigned SrcReg, bool IsSigned);
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unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
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// Call handling routines.
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private:
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@ -786,6 +793,260 @@ bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
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return true;
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}
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// Attempt to fast-select a floating-point extend instruction.
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bool PPCFastISel::SelectFPExt(const Instruction *I) {
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::f32 || DestVT != MVT::f64)
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (!SrcReg)
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return false;
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// No code is generated for a FP extend.
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UpdateValueMap(I, SrcReg);
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return true;
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}
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// Attempt to fast-select a floating-point truncate instruction.
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bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
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Value *Src = I->getOperand(0);
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EVT SrcVT = TLI.getValueType(Src->getType(), true);
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EVT DestVT = TLI.getValueType(I->getType(), true);
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if (SrcVT != MVT::f64 || DestVT != MVT::f32)
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (!SrcReg)
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return false;
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// Round the result to single precision.
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unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP), DestReg)
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.addReg(SrcReg);
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UpdateValueMap(I, DestReg);
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return true;
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}
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// Move an i32 or i64 value in a GPR to an f64 value in an FPR.
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// FIXME: When direct register moves are implemented (see PowerISA 2.08),
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// those should be used instead of moving via a stack slot when the
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// subtarget permits.
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// FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
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// stack slot and 4-byte store/load sequence. Or just sext the 4-byte
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// case to 8 bytes which produces tighter code but wastes stack space.
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unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
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bool IsSigned) {
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// If necessary, extend 32-bit int to 64-bit.
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if (SrcVT == MVT::i32) {
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unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
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if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
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return 0;
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SrcReg = TmpReg;
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}
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// Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
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Address Addr;
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Addr.BaseType = Address::FrameIndexBase;
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Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
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// Store the value from the GPR.
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if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
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return 0;
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// Load the integer value into an FPR. The kind of load used depends
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// on a number of conditions.
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unsigned LoadOpc = PPC::LFD;
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if (SrcVT == MVT::i32) {
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Addr.Offset = 4;
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if (!IsSigned)
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LoadOpc = PPC::LFIWZX;
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else if (PPCSubTarget.hasLFIWAX())
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LoadOpc = PPC::LFIWAX;
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}
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const TargetRegisterClass *RC = &PPC::F8RCRegClass;
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unsigned ResultReg = 0;
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if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
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return 0;
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return ResultReg;
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}
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// Attempt to fast-select an integer-to-floating-point conversion.
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bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
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MVT DstVT;
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Type *DstTy = I->getType();
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if (!isTypeLegal(DstTy, DstVT))
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return false;
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if (DstVT != MVT::f32 && DstVT != MVT::f64)
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return false;
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Value *Src = I->getOperand(0);
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EVT SrcEVT = TLI.getValueType(Src->getType(), true);
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if (!SrcEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
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SrcVT != MVT::i32 && SrcVT != MVT::i64)
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (SrcReg == 0)
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return false;
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// We can only lower an unsigned convert if we have the newer
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// floating-point conversion operations.
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if (!IsSigned && !PPCSubTarget.hasFPCVT())
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return false;
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// FIXME: For now we require the newer floating-point conversion operations
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// (which are present only on P7 and A2 server models) when converting
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// to single-precision float. Otherwise we have to generate a lot of
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// fiddly code to avoid double rounding. If necessary, the fiddly code
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// can be found in PPCTargetLowering::LowerINT_TO_FP().
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if (DstVT == MVT::f32 && !PPCSubTarget.hasFPCVT())
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return false;
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// Extend the input if necessary.
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if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
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unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
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if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
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return false;
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SrcVT = MVT::i64;
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SrcReg = TmpReg;
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}
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// Move the integer value to an FPR.
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unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
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if (FPReg == 0)
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return false;
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// Determine the opcode for the conversion.
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const TargetRegisterClass *RC = &PPC::F8RCRegClass;
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unsigned DestReg = createResultReg(RC);
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unsigned Opc;
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if (DstVT == MVT::f32)
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Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
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else
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Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
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// Generate the convert.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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.addReg(FPReg);
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UpdateValueMap(I, DestReg);
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return true;
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}
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// Move the floating-point value in SrcReg into an integer destination
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// register, and return the register (or zero if we can't handle it).
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// FIXME: When direct register moves are implemented (see PowerISA 2.08),
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// those should be used instead of moving via a stack slot when the
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// subtarget permits.
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unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
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unsigned SrcReg, bool IsSigned) {
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// Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
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// Note that if have STFIWX available, we could use a 4-byte stack
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// slot for i32, but this being fast-isel we'll just go with the
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// easiest code gen possible.
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Address Addr;
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Addr.BaseType = Address::FrameIndexBase;
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Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
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// Store the value from the FPR.
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if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
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return 0;
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// Reload it into a GPR. If we want an i32, modify the address
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// to have a 4-byte offset so we load from the right place.
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if (VT == MVT::i32)
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Addr.Offset = 4;
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// Look at the currently assigned register for this instruction
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// to determine the required register class.
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unsigned AssignedReg = FuncInfo.ValueMap[I];
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const TargetRegisterClass *RC =
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AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
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unsigned ResultReg = 0;
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if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
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return 0;
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return ResultReg;
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}
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// Attempt to fast-select a floating-point-to-integer conversion.
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bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
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MVT DstVT, SrcVT;
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Type *DstTy = I->getType();
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if (!isTypeLegal(DstTy, DstVT))
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return false;
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if (DstVT != MVT::i32 && DstVT != MVT::i64)
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return false;
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Value *Src = I->getOperand(0);
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Type *SrcTy = Src->getType();
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if (!isTypeLegal(SrcTy, SrcVT))
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return false;
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if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
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return false;
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unsigned SrcReg = getRegForValue(Src);
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if (SrcReg == 0)
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return false;
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// Convert f32 to f64 if necessary. This is just a meaningless copy
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// to get the register class right. COPY_TO_REGCLASS is needed since
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// a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
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const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
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if (InRC == &PPC::F4RCRegClass) {
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unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
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.addReg(SrcReg).addImm(PPC::F8RCRegClassID);
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SrcReg = TmpReg;
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}
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// Determine the opcode for the conversion, which takes place
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// entirely within FPRs.
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unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
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unsigned Opc;
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if (DstVT == MVT::i32)
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if (IsSigned)
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Opc = PPC::FCTIWZ;
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else
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Opc = PPCSubTarget.hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
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else
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Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
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// Generate the convert.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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.addReg(SrcReg);
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// Now move the integer value from a float register to an integer register.
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unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
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if (IntReg == 0)
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return false;
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UpdateValueMap(I, IntReg);
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return true;
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}
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// Attempt to fast-select a binary integer operation that isn't already
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// handled automatically.
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bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
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@ -1135,6 +1396,18 @@ bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
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return SelectBranch(I);
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case Instruction::IndirectBr:
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return SelectIndirectBr(I);
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case Instruction::FPExt:
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return SelectFPExt(I);
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case Instruction::FPTrunc:
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return SelectFPTrunc(I);
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case Instruction::SIToFP:
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return SelectIToFP(I, /*IsSigned*/ true);
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case Instruction::UIToFP:
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return SelectIToFP(I, /*IsSigned*/ false);
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case Instruction::FPToSI:
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return SelectFPToI(I, /*IsSigned*/ true);
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case Instruction::FPToUI:
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return SelectFPToI(I, /*IsSigned*/ false);
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case Instruction::Add:
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return SelectBinaryIntOp(I, ISD::ADD);
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case Instruction::Or:
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@ -69,6 +69,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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@ -532,6 +533,7 @@ static bool usesIXAddr(const MachineInstr &MI) {
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default:
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return false;
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case PPC::LWA:
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case PPC::LWA_32:
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case PPC::LD:
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case PPC::STD:
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return true;
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305
test/CodeGen/PowerPC/fast-isel-conversion.ll
Normal file
305
test/CodeGen/PowerPC/fast-isel-conversion.ll
Normal file
@ -0,0 +1,305 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; Test sitofp
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define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i64
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%b.addr = alloca float, align 4
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%conv = sitofp i64 %a to float
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i32
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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; ELF64: std
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; ELF64: lfiwax
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; ELF64: fcfids
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i16
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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; ELF64: extsh
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i8
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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; ELF64: extsb
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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; ELF64: std
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; ELF64: lfiwax
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; ELF64: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i64
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = sitofp i64 %a to double
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfid
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: sitofp_double_i16
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = sitofp i16 %a to double
|
||||
; ELF64: extsh
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfid
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: sitofp_double_i8
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = sitofp i8 %a to double
|
||||
; ELF64: extsb
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfid
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test uitofp
|
||||
|
||||
define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_single_i64
|
||||
%b.addr = alloca float, align 4
|
||||
%conv = uitofp i64 %a to float
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidus
|
||||
store float %conv, float* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_single_i32
|
||||
%b.addr = alloca float, align 4
|
||||
%conv = uitofp i32 %a to float
|
||||
; ELF64: std
|
||||
; ELF64: lfiwzx
|
||||
; ELF64: fcfidus
|
||||
store float %conv, float* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_single_i16
|
||||
%b.addr = alloca float, align 4
|
||||
%conv = uitofp i16 %a to float
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidus
|
||||
store float %conv, float* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_single_i8(i8 %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_single_i8
|
||||
%b.addr = alloca float, align 4
|
||||
%conv = uitofp i8 %a to float
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidus
|
||||
store float %conv, float* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_double_i64
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = uitofp i64 %a to double
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidu
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_double_i32
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = uitofp i32 %a to double
|
||||
; ELF64: std
|
||||
; ELF64: lfiwzx
|
||||
; ELF64: fcfidu
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_double_i16
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = uitofp i16 %a to double
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidu
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: uitofp_double_i8
|
||||
%b.addr = alloca double, align 8
|
||||
%conv = uitofp i8 %a to double
|
||||
; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
|
||||
; ELF64: std
|
||||
; ELF64: lfd
|
||||
; ELF64: fcfidu
|
||||
store double %conv, double* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test fptosi
|
||||
|
||||
define void @fptosi_float_i32(float %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptosi_float_i32
|
||||
%b.addr = alloca i32, align 4
|
||||
%conv = fptosi float %a to i32
|
||||
; ELF64: fctiwz
|
||||
; ELF64: stfd
|
||||
; ELF64: lwa
|
||||
store i32 %conv, i32* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptosi_float_i64(float %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptosi_float_i64
|
||||
%b.addr = alloca i64, align 4
|
||||
%conv = fptosi float %a to i64
|
||||
; ELF64: fctidz
|
||||
; ELF64: stfd
|
||||
; ELF64: ld
|
||||
store i64 %conv, i64* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptosi_double_i32(double %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptosi_double_i32
|
||||
%b.addr = alloca i32, align 8
|
||||
%conv = fptosi double %a to i32
|
||||
; ELF64: fctiwz
|
||||
; ELF64: stfd
|
||||
; ELF64: lwa
|
||||
store i32 %conv, i32* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptosi_double_i64(double %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptosi_double_i64
|
||||
%b.addr = alloca i64, align 8
|
||||
%conv = fptosi double %a to i64
|
||||
; ELF64: fctidz
|
||||
; ELF64: stfd
|
||||
; ELF64: ld
|
||||
store i64 %conv, i64* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test fptoui
|
||||
|
||||
define void @fptoui_float_i32(float %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptoui_float_i32
|
||||
%b.addr = alloca i32, align 4
|
||||
%conv = fptoui float %a to i32
|
||||
; ELF64: fctiwuz
|
||||
; ELF64: stfd
|
||||
; ELF64: lwz
|
||||
store i32 %conv, i32* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptoui_float_i64(float %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptoui_float_i64
|
||||
%b.addr = alloca i64, align 4
|
||||
%conv = fptoui float %a to i64
|
||||
; ELF64: fctiduz
|
||||
; ELF64: stfd
|
||||
; ELF64: ld
|
||||
store i64 %conv, i64* %b.addr, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptoui_double_i32(double %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptoui_double_i32
|
||||
%b.addr = alloca i32, align 8
|
||||
%conv = fptoui double %a to i32
|
||||
; ELF64: fctiwuz
|
||||
; ELF64: stfd
|
||||
; ELF64: lwz
|
||||
store i32 %conv, i32* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @fptoui_double_i64(double %a) nounwind ssp {
|
||||
entry:
|
||||
; ELF64: fptoui_double_i64
|
||||
%b.addr = alloca i64, align 8
|
||||
%conv = fptoui double %a to i64
|
||||
; ELF64: fctiduz
|
||||
; ELF64: stfd
|
||||
; ELF64: ld
|
||||
store i64 %conv, i64* %b.addr, align 8
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user