From 9bdd78501484a1add2d8a757fd29960dd9fc9de7 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Mon, 10 Jun 2013 23:20:58 +0000 Subject: [PATCH] ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one. Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARM.td | 3 ++- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 19 ++++++++++++++++++ .../ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 2 ++ test/MC/ARM/arm-thumb-cpus-default.s | 13 ++++++++++++ test/MC/ARM/arm-thumb-cpus.s | 20 +++++++++++++++++++ test/MC/ARM/elf-thumbfunc-reloc.s | 2 +- test/MC/ARM/mapping-within-section.s | 2 +- test/MC/ARM/multi-section-mapping.s | 2 +- 8 files changed, 59 insertions(+), 4 deletions(-) create mode 100644 test/MC/ARM/arm-thumb-cpus-default.s create mode 100644 test/MC/ARM/arm-thumb-cpus.s diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6e9d62fdea1..1bc9d6b410d 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -38,7 +38,8 @@ def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", - "Does not support ARM mode execution">; + "Does not support ARM mode execution", + [ModeThumb]>; def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", "Enable half-precision floating point">; def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true", diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index ce935b9817c..314d37d7d58 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -152,12 +152,19 @@ class ARMAsmParser : public MCTargetAsmParser { bool isThumbTwo() const { return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); } + bool hasThumb() const { + return STI.getFeatureBits() & ARM::HasV4TOps; + } bool hasV6Ops() const { return STI.getFeatureBits() & ARM::HasV6Ops; } bool hasV7Ops() const { return STI.getFeatureBits() & ARM::HasV7Ops; } + bool hasARM() const { + return !(STI.getFeatureBits() & ARM::FeatureNoARM); + } + void SwitchMode() { unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); setAvailableFeatures(FB); @@ -7816,6 +7823,9 @@ bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { return Error(L, "unexpected token in directive"); Parser.Lex(); + if (!hasThumb()) + return Error(L, "target does not support Thumb mode"); + if (!isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); @@ -7829,6 +7839,9 @@ bool ARMAsmParser::parseDirectiveARM(SMLoc L) { return Error(L, "unexpected token in directive"); Parser.Lex(); + if (!hasARM()) + return Error(L, "target does not support ARM mode"); + if (isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); @@ -7918,10 +7931,16 @@ bool ARMAsmParser::parseDirectiveCode(SMLoc L) { Parser.Lex(); if (Val == 16) { + if (!hasThumb()) + return Error(L, "target does not support Thumb mode"); + if (!isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); } else { + if (!hasARM()) + return Error(L, "target does not support ARM mode"); + if (isThumb()) SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 164f57b2d05..14fd03fad8e 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -61,6 +61,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { if (Len >= Idx+2 && TT[Idx+1] == 'm') { + isThumb = true; if (NoCPU) // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass"; @@ -99,6 +100,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) { if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') ARMArchFeature = "+v6t2"; else if (Len >= Idx+2 && TT[Idx+1] == 'm') { + isThumb = true; if (NoCPU) // v6m: FeatureNoARM, FeatureMClass ARMArchFeature = "+v6,+noarm,+mclass"; diff --git a/test/MC/ARM/arm-thumb-cpus-default.s b/test/MC/ARM/arm-thumb-cpus-default.s new file mode 100644 index 00000000000..636ee3c5057 --- /dev/null +++ b/test/MC/ARM/arm-thumb-cpus-default.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc -show-encoding -arch=arm < %s | FileCheck %s --check-prefix=CHECK-ARM-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv4t < %s | FileCheck %s --check-prefix=CHECK-ARM-THUMB +@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s| FileCheck %s --check-prefix=CHECK-ARM-THUMB +@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv7m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv6m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + + @ Make sure the architecture chosen by LLVM defaults to a compatible + @ ARM/Thumb mode. + movs r0, r0 +@ CHECK-ARM-THUMB: movs r0, r0 @ encoding: [0x00,0x00,0xb0,0xe1] +@ CHECK-ARM-ONLY: movs r0, r0 @ encoding: [0x00,0x00,0xb0,0xe1] +@ CHECK-THUMB-ONLY: movs r0, r0 @ encoding: [0x00,0x00] diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s new file mode 100644 index 00000000000..c15e8078186 --- /dev/null +++ b/test/MC/ARM/arm-thumb-cpus.s @@ -0,0 +1,20 @@ +@ RUN: llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB +@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB +@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + + @ Make sure correct diagnostics are given for CPUs without support for + @ one or other of the execution states. + .thumb + .arm + .code 16 + .code 32 +@ CHECK-ARM-THUMB-NOT: target does not support + +@ CHECK-ARM-ONLY: target does not support Thumb mode +@ CHECK-ARM-ONLY: target does not support Thumb mode + +@ CHECK-THUMB-ONLY: target does not support ARM mode +@ CHECK-THUMB-ONLY: target does not support ARM mode diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s index de3594e1ce1..614702012f0 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.s +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -1,5 +1,5 @@ @@ test st_value bit 0 of thumb function -@ RUN: llvm-mc %s -triple=arm-freebsd-eabi -filetype=obj -o - | \ +@ RUN: llvm-mc %s -triple=armv4t-freebsd-eabi -filetype=obj -o - | \ @ RUN: llvm-readobj -r | FileCheck %s diff --git a/test/MC/ARM/mapping-within-section.s b/test/MC/ARM/mapping-within-section.s index 56dd6ef07e7..b1379d28a36 100644 --- a/test/MC/ARM/mapping-within-section.s +++ b/test/MC/ARM/mapping-within-section.s @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple=arm-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s .text @ $a at 0x0000 diff --git a/test/MC/ARM/multi-section-mapping.s b/test/MC/ARM/multi-section-mapping.s index f7c4e89a85e..2b1b0efab53 100644 --- a/test/MC/ARM/multi-section-mapping.s +++ b/test/MC/ARM/multi-section-mapping.s @@ -1,4 +1,4 @@ -@ RUN: llvm-mc -triple=arm-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj < %s | llvm-objdump -t - | FileCheck %s .text add r0, r0, r0