6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-15 23:31:37 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Don't display the GDS bit.

Browse Source 
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204270 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-03-19 22:19:43 +00:00
parent 6d1781733d
commit 9c0b2d08d3
6 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/R600/SIInstrInfo.td
View File

@ -395,7 +395,7 @@ class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
op,
(outs regClass:$vdst),
(ins i1imm:$gds, VReg_32:$addr, i16imm:$offset),
asm#" $gds, $vdst, $addr, $offset, [M0]",
asm#" $vdst, $addr, $offset, [M0]",
[]> {
let data0 = 0;
let data1 = 0;
@ -407,7 +407,7 @@ class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
op,
(outs),
(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
asm#" $gds, $addr, $data0, $offset [M0]",
asm#" $addr, $data0, $offset [M0]",
[]> {
let data1 = 0;
let mayStore = 1;
@ -419,7 +419,7 @@ class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc> : DS_1A <
op,
(outs rc:$vdst),
(ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, i16imm:$offset),
asm#" $gds, $vdst, $addr, $data0, $offset, [M0]",
asm#" $vdst, $addr, $data0, $offset, [M0]",
[]> {
let data1 = 0;

2
test/CodeGen/R600/32-bit-local-address-space.ll
View File

@ -69,7 +69,7 @@ define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %
; CHECK-LABEL: @infer_ptr_alignment_global_offset:
; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0
; CHECK: DS_READ_B32 v{{[0-9]+}}, 0, [[REG]]
; CHECK: DS_READ_B32 v{{[0-9]+}}, [[REG]]
define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
%val = load float addrspace(3)* @g_lds
store float %val, float addrspace(1)* %out

4
test/CodeGen/R600/atomic_load_add.ll
View File

@ -4,7 +4,7 @@
; R600-CHECK-LABEL: @atomic_add_local
; R600-CHECK: LDS_ADD *
; SI-CHECK-LABEL: @atomic_add_local
; SI-CHECK: DS_ADD_U32_RTN 0
; SI-CHECK: DS_ADD_U32_RTN
define void @atomic_add_local(i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst
@ -14,7 +14,7 @@ entry:
; R600-CHECK-LABEL: @atomic_add_ret_local
; R600-CHECK: LDS_ADD_RET *
; SI-CHECK-LABEL: @atomic_add_ret_local
; SI-CHECK: DS_ADD_U32_RTN 0
; SI-CHECK: DS_ADD_U32_RTN
define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst

4
test/CodeGen/R600/atomic_load_sub.ll
View File

@ -4,7 +4,7 @@
; R600-CHECK-LABEL: @atomic_sub_local
; R600-CHECK: LDS_SUB *
; SI-CHECK-LABEL: @atomic_sub_local
; SI-CHECK: DS_SUB_U32_RTN 0
; SI-CHECK: DS_SUB_U32_RTN
define void @atomic_sub_local(i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst
@ -14,7 +14,7 @@ entry:
; R600-CHECK-LABEL: @atomic_sub_ret_local
; R600-CHECK: LDS_SUB_RET *
; SI-CHECK-LABEL: @atomic_sub_ret_local
; SI-CHECK: DS_SUB_U32_RTN 0
; SI-CHECK: DS_SUB_U32_RTN
define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) {
entry:
%0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst

8
test/CodeGen/R600/local-memory-two-objects.ll
View File

@ -17,8 +17,8 @@
; this consistently on evergreen GPUs.
; EG-CHECK: LDS_WRITE
; EG-CHECK: LDS_WRITE
; SI-CHECK: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
; SI-CHECK-NOT: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW]]
; SI-CHECK: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
; SI-CHECK-NOT: DS_WRITE_B32 {{v[0-9]*}}, v[[ADDRW]]
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
@ -27,8 +27,8 @@
; Make sure the lds reads are using different addresses.
; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR:v[0-9]+]]
; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR]]
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]]
; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, [[ADDRR]]
define void @local_memory_two_objects(i32 addrspace(1)* %out) {
entry:

4
test/CodeGen/R600/local-memory.ll
View File

@ -18,7 +18,7 @@
; EG-CHECK: LDS_WRITE
; SI-CHECK-NOT: S_WQM_B64
; SI-CHECK: DS_WRITE_B32 0
; SI-CHECK: DS_WRITE_B32
; GROUP_BARRIER must be the last instruction in a clause
; EG-CHECK: GROUP_BARRIER
@ -26,7 +26,7 @@
; SI-CHECK: S_BARRIER
; EG-CHECK: LDS_READ_RET
; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0
; SI-CHECK: DS_READ_B32 {{v[0-9]+}},
define void @local_memory(i32 addrspace(1)* %out) {
entry: