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[x86] Teach the new vector shuffle lowering to use the AVX VPERMILPS

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instruction for single-vector floating point shuffles. This in turn
allows the shuffles to fold a load into the instruction which is one of
the common regressions hit with the new shuffle lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218190 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-09-20 20:52:07 +00:00
parent 1c1bde666c
commit 9c7ffd20df
2 changed files with 90 additions and 24 deletions
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14
lib/Target/X86/X86ISelLowering.cpp
View File

@ -7772,11 +7772,19 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
int NumV2Elements =
std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
if (NumV2Elements == 0)
// Straight shuffle of a single input vector. We pass the input vector to
// both operands to simulate this with a SHUFPS.
if (NumV2Elements == 0) {
if (Subtarget->hasAVX()) {
// If we have AVX, we can use VPERMILPS which will allow folding a load
// into the shuffle.
return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
getV4X86ShuffleImm8ForMask(Mask, DAG));
}
// Otherwise, use a straight shuffle of a single input vector. We pass the
// input vector to both operands to simulate this with a SHUFPS.
return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
getV4X86ShuffleImm8ForMask(Mask, DAG));
}
// Use dedicated unpack instructions for masks that match their pattern.
if (isShuffleEquivalent(Mask, 0, 4, 1, 5))

100
test/CodeGen/X86/vector-shuffle-128-v4.ll
View File

@ -73,51 +73,93 @@ define <4 x i32> @shuffle_v4i32_2121(<4 x i32> %a, <4 x i32> %b) {
}
define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_0001
; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_0001
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_0001
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,0,1]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_0020
; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_0020
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_0020
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,2,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_0300
; ALL: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_0300
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_0300
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,3,0,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_1000
; ALL: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_1000
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_1000
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[1,0,0,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_2200
; ALL: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_2200
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_2200
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[2,2,0,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_3330
; ALL: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_3330
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_3330
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,3,3,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
; ALL-LABEL: @shuffle_v4f32_3210
; ALL: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
; ALL-NEXT: retq
; SSE-LABEL: @shuffle_v4f32_3210
; SSE: # BB#0:
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_v4f32_3210
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,2,1,0]
; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %shuffle
}
@ -805,3 +847,19 @@ define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
%shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
ret <4 x float> %shuffle
}
define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
; SSE-LABEL: @shuffle_mem_v4f32_3210
; SSE: # BB#0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
; SSE-NEXT: retq
;
; AVX-LABEL: @shuffle_mem_v4f32_3210
; AVX: # BB#0:
; AVX-NEXT: vpermilps {{.*}} # xmm0 = mem[3,2,1,0]
; AVX-NEXT: retq
%a = load <4 x float>* %ptr
%shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x float> %shuffle
}