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Teach instcombine about the rest of the SSE and SSE2 conversion
intrinsics element dependencies. Reviewed by Nick. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123161 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -540,9 +540,16 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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return new StoreInst(II->getArgOperand(1), Ptr);
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}
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break;
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case Intrinsic::x86_sse_cvttss2si: {
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// These intrinsics only demands the 0th element of its input vector. If
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case Intrinsic::x86_sse_cvtss2si:
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case Intrinsic::x86_sse_cvtss2si64:
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case Intrinsic::x86_sse_cvttss2si:
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case Intrinsic::x86_sse_cvttss2si64:
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case Intrinsic::x86_sse2_cvtsd2si:
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case Intrinsic::x86_sse2_cvtsd2si64:
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case Intrinsic::x86_sse2_cvttsd2si:
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case Intrinsic::x86_sse2_cvttsd2si64: {
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// These intrinsics only demand the 0th element of their input vectors. If
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// we can simplify the input based on that, do so now.
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unsigned VWidth =
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cast<VectorType>(II->getArgOperand(0)->getType())->getNumElements();
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@ -555,7 +562,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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}
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break;
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}
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case Intrinsic::ppc_altivec_vperm:
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// Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
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if (ConstantVector *Mask = dyn_cast<ConstantVector>(II->getArgOperand(2))) {
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@ -36,6 +36,54 @@ define i32 @test2(float %f) {
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ret i32 %tmp21
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}
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define i64 @test3(float %f, double %d) {
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; CHECK: @test3
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; CHECK-NOT: insertelement {{.*}} 0.00
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; CHECK: ret
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entry:
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%v00 = insertelement <4 x float> undef, float %f, i32 0
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%v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1
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%v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2
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%v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3
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%tmp0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> %v03)
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%v10 = insertelement <4 x float> undef, float %f, i32 0
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%v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1
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%v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2
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%v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3
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%tmp1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %v13)
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%v20 = insertelement <4 x float> undef, float %f, i32 0
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%v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1
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%v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2
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%v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3
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%tmp2 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %v23)
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%v30 = insertelement <4 x float> undef, float %f, i32 0
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%v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1
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%v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2
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%v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3
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%tmp3 = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %v33)
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%v40 = insertelement <2 x double> undef, double %d, i32 0
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%v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1
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%tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
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%v50 = insertelement <2 x double> undef, double %d, i32 0
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%v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1
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%tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
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%v60 = insertelement <2 x double> undef, double %d, i32 0
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%v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1
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%tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
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%v70 = insertelement <2 x double> undef, double %d, i32 0
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%v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1
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%tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
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%tmp8 = add i32 %tmp0, %tmp2
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%tmp9 = add i32 %tmp4, %tmp6
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%tmp10 = add i32 %tmp8, %tmp9
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%tmp11 = sext i32 %tmp10 to i64
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%tmp12 = add i64 %tmp1, %tmp3
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%tmp13 = add i64 %tmp5, %tmp7
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%tmp14 = add i64 %tmp12, %tmp13
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%tmp15 = add i64 %tmp11, %tmp14
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ret i64 %tmp15
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}
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define void @get_image() nounwind {
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; CHECK: @get_image
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; CHECK-NOT: extractelement
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@ -80,4 +128,11 @@ declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
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declare i32 @llvm.x86.sse.cvtss2si(<4 x float>)
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declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>)
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declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>)
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declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
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declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
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