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Gabor points out that we can't spell. :)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-24 07:12:19 +00:00
parent 9a0c9551fa
commit 9d5da1d96c
3 changed files with 5 additions and 5 deletions
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2
lib/Target/PowerPC/PPCInstrInfo.td
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@ -659,7 +659,7 @@ def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
///
/// Note that these are defined as pseudo-ops on the PPC970 because they are
/// often coallesced away and we don't want the dispatch group builder to think
/// often coalesced away and we don't want the dispatch group builder to think
/// that they will fill slots (which could cause the load of a LSU reject to
/// sneak into a d-group with a store).
def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),

4
lib/Target/X86/README.txt
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@ -547,7 +547,7 @@ feasible.
//===---------------------------------------------------------------------===//
Teach the coallescer to commute 2-addr instructions, allowing us to eliminate
Teach the coalescer to commute 2-addr instructions, allowing us to eliminate
the reg-reg copy in this example:
float foo(int *x, float *y, unsigned c) {
@ -642,7 +642,7 @@ lambda, siod, optimizer-eval, ackermann, hash2, nestedloop, strcat, and Treesor.
//===---------------------------------------------------------------------===//
Teach the coallescer to coales vregs of different register classes. e.g. FR32 /
Teach the coalescer to coalesce vregs of different register classes. e.g. FR32 /
FR64 to VR128.
//===---------------------------------------------------------------------===//

4
lib/Target/X86/X86ISelLowering.cpp
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@ -660,10 +660,10 @@ static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
// EDX". Anything more is illegal.
//
// FIXME: The linscan register allocator currently has problem with
// coallescing. At the time of this writing, whenever it decides to coallesce
// coalescing. At the time of this writing, whenever it decides to coalesce
// a physreg with a virtreg, this increases the size of the physreg's live
// range, and the live range cannot ever be reduced. This causes problems if
// too many physregs are coalleced with virtregs, which can cause the register
// too many physregs are coaleced with virtregs, which can cause the register
// allocator to wedge itself.
//
// This code triggers this problem more often if we pass args in registers,