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Fold preceding / trailing base inc / dec into the single load / store as well.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-06-03 06:14:58 +00:00
parent 95299c194d
commit 9d5fb981b0
2 changed files with 21 additions and 2 deletions
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11
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -697,7 +697,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
// LDM/STM ops. // LDM/STM ops.
for (unsigned i = 0, e = MBBII.size(); i < e; ++i) for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI)) if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI))
NumMerges++; ++NumMerges;
NumMerges += MBBII.size(); NumMerges += MBBII.size();
// Try folding preceeding/trailing base inc/dec into those load/store // Try folding preceeding/trailing base inc/dec into those load/store
@ -705,10 +705,17 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
for (unsigned i = 0; i != NumMemOps; ++i) for (unsigned i = 0; i != NumMemOps; ++i)
if (!MemOps[i].Merged) if (!MemOps[i].Merged)
if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI)) if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
NumMerges++; ++NumMerges;
// RS may be pointing to an instruction that's deleted. // RS may be pointing to an instruction that's deleted.
RS->skipTo(prior(MBBI)); RS->skipTo(prior(MBBI));
} else if (NumMemOps == 1) {
// Try folding preceeding/trailing base inc/dec into the single
// load/store.
if (mergeBaseUpdateLoadStore(MBB, MemOps[0].MBBI, TII, Advance, MBBI)) {
++NumMerges;
RS->skipTo(prior(MBBI));
}
} }
CurrBase = 0; CurrBase = 0;

12
test/CodeGen/ARM/str_pre-2.ll Normal file
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@ -0,0 +1,12 @@
; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {str.*\\!}
; RUN: llvm-as < %s | llc -mtriple=arm-linux-gnu | grep {ldr.*\\\[.*\], #+4}
@b = external global i64*
define i64 @t(i64 %a) nounwind readonly {
entry:
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
%2 = mul i64 %1, %a
ret i64 %2
}