Implement register class inflation.

When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110703 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/CalcSpillWeights.h

@@ -32,10 +32,10 @@ namespace llvm {
                    const MachineLoopInfo &loops) :
       mf_(mf), lis_(lis), loops_(loops) {}
 
-    /// CalculateRegClass - recompute the register class for li from its uses.
+    /// CalculateRegClass - recompute the register class for reg from its uses.
     /// Since the register class can affect the allocation hint, this function
     /// should be called before CalculateWeightAndHint if both are called.
-    void CalculateRegClass(LiveInterval &li);
+    void CalculateRegClass(unsigned reg);
 
     /// CalculateWeightAndHint - (re)compute li's spill weight and allocation
     /// hint.

include/llvm/Target/TargetInstrDesc.h

@@ -152,6 +152,12 @@ public:
     return -1;
   }
 
+  /// getRegClass - Returns the register class constraint for OpNum, or NULL.
+  const TargetRegisterClass *getRegClass(unsigned OpNum,
+                                         const TargetRegisterInfo *TRI) const {
+    return OpNum < NumOperands ? OpInfo[OpNum].getRegClass(TRI) : 0;
+  }
+
   /// getOpcode - Return the opcode number for this descriptor.
   unsigned getOpcode() const {
     return Opcode;

lib/CodeGen/CalcSpillWeights.cpp

@@ -174,3 +174,44 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
   lis_.normalizeSpillWeight(li);
 }
 
+void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
+  MachineRegisterInfo &mri = mf_.getRegInfo();
+  const TargetRegisterInfo *tri = mf_.getTarget().getRegisterInfo();
+  const TargetRegisterClass *orc = mri.getRegClass(reg);
+  SmallPtrSet<const TargetRegisterClass*,8> rcs;
+
+  for (MachineRegisterInfo::reg_nodbg_iterator I = mri.reg_nodbg_begin(reg),
+       E = mri.reg_nodbg_end(); I != E; ++I)
+    if (const TargetRegisterClass *rc =
+                                I->getDesc().getRegClass(I.getOperandNo(), tri))
+      rcs.insert(rc);
+
+  // If we found no regclass constraints, just leave reg as is.
+  // In theory, we could inflate to the largest superclass of reg's existing
+  // class, but that might not be legal for the current cpu setting.
+  // This could happen if reg is only used by COPY instructions, so we may need
+  // to improve on this.
+  if (rcs.empty()) {
+    DEBUG(dbgs() << "Not inflating unconstrained" << orc->getName() << ":%reg"
+                 << reg << ".\n");
+    return;
+  }
+
+  // Compute the intersection of all classes in rcs.
+  // This ought to be independent of iteration order, but if the target register
+  // classes don't form a proper algebra, it is possible to get different
+  // results. The solution is to make sure the intersection of any two register
+  // classes is also a register class or the null set.
+  const TargetRegisterClass *rc = 0;
+  for (SmallPtrSet<const TargetRegisterClass*,8>::iterator I = rcs.begin(),
+         E = rcs.end(); I != E; ++I) {
+    rc = rc ? getCommonSubClass(rc, *I) : *I;
+    assert(rc && "Incompatible regclass constraints found");
+  }
+
+  if (rc == orc)
+    return;
+  DEBUG(dbgs() << "Inflating " << orc->getName() << ":%reg" << reg << " to "
+               << rc->getName() <<".\n");
+  mri.setRegClass(reg, rc);
+}

lib/CodeGen/SplitKit.cpp

@@ -571,6 +571,7 @@ void SplitEditor::rewrite() {
   VirtRegAuxInfo vrai(vrm_.getMachineFunction(), lis_, sa_.loops_);
   for (unsigned i = firstInterval, e = intervals_.size(); i != e; ++i) {
     LiveInterval &li = *intervals_[i];
+    vrai.CalculateRegClass(li.reg);
     vrai.CalculateWeightAndHint(li);
   }
 }