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sched: Avoid trivially redundant DAG edges. Take the one with higher latency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158379 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -117,8 +117,9 @@ namespace llvm {
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}
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}
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bool operator==(const SDep &Other) const {
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if (Dep != Other.Dep || Latency != Other.Latency) return false;
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/// Return true if the specified SDep is equivalent except for latency.
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bool overlaps(const SDep &Other) const {
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if (Dep != Other.Dep) return false;
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switch (Dep.getInt()) {
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case Data:
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case Anti:
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@ -133,6 +134,10 @@ namespace llvm {
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llvm_unreachable("Invalid dependency kind!");
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}
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bool operator==(const SDep &Other) const {
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return overlaps(Other) && Latency == Other.Latency;
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}
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bool operator!=(const SDep &Other) const {
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return !operator==(Other);
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}
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@ -64,10 +64,27 @@ const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
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/// specified node.
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bool SUnit::addPred(const SDep &D) {
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// If this node already has this depenence, don't add a redundant one.
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for (SmallVector<SDep, 4>::const_iterator I = Preds.begin(), E = Preds.end();
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I != E; ++I)
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if (*I == D)
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for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end();
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I != E; ++I) {
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if (I->overlaps(D)) {
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// Extend the latency if needed. Equivalent to removePred(I) + addPred(D).
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if (I->getLatency() < D.getLatency()) {
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SUnit *PredSU = I->getSUnit();
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// Find the corresponding successor in N.
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SDep ForwardD = *I;
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ForwardD.setSUnit(this);
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for (SmallVector<SDep, 4>::iterator II = PredSU->Succs.begin(),
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EE = PredSU->Succs.end(); II != EE; ++II) {
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if (*II == ForwardD) {
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II->setLatency(D.getLatency());
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break;
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}
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}
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I->setLatency(D.getLatency());
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}
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return false;
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}
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}
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// Now add a corresponding succ to N.
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SDep P = D;
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P.setSUnit(this);
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