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Move some methods to a new MCInstrDesc.cpp file to allow includes to be trimmed. NFC.

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MCInstrDesc.h includes things like MCInst.h which i can now remove after this.  That will be a future commit.

Reviewed by Jim Grosbach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pete Cooper
2015-05-15 21:29:43 +00:00
parent e892415f25
commit 9e514203d1
3 changed files with 79 additions and 47 deletions
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57
include/llvm/MC/MCInstrDesc.h
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@@ -165,16 +165,7 @@ public:
/// \brief Returns true if a certain instruction is deprecated and if so
/// returns the reason in \p Info.
bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info) const {
if (ComplexDeprecationInfo)
return ComplexDeprecationInfo(MI, STI, Info);
if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
// FIXME: it would be nice to include the subtarget feature here.
Info = "deprecated";
return true;
}
return false;
}
std::string &Info) const;
/// \brief Return the opcode number for this descriptor.
unsigned getOpcode() const { return Opcode; }
@@ -257,25 +248,7 @@ public:
/// \brief Return true if this is a branch or an instruction which directly
/// writes to the program counter. Considered 'may' affect rather than
/// 'does' affect as things like predication are not taken into account.
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
if (isBranch() || isCall() || isReturn() || isIndirectBranch())
return true;
unsigned PC = RI.getProgramCounter();
if (PC == 0)
return false;
if (hasDefOfPhysReg(MI, PC, RI))
return true;
// A variadic instruction may define PC in the variable operand list.
// There's currently no indication of which entries in a variable
// list are defs and which are uses. While that's the case, this function
// needs to assume they're defs in order to be conservatively correct.
for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
if (MI.getOperand(i).isReg() &&
RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
return true;
}
return false;
}
bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
/// \brief Return true if this instruction has a predicate operand
/// that controls execution. It may be set to 'always', or may be set to other
@@ -532,24 +505,7 @@ public:
/// \brief Return true if this instruction implicitly
/// defines the specified physical register.
bool hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI = nullptr) const {
if (const uint16_t *ImpDefs = ImplicitDefs)
for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
return true;
return false;
}
/// \brief Return true if this instruction defines the specified physical
/// register, either explicitly or implicitly.
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
const MCRegisterInfo &RI) const {
for (int i = 0, e = NumDefs; i != e; ++i)
if (MI.getOperand(i).isReg() &&
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
return true;
return hasImplicitDefOfPhysReg(Reg, &RI);
}
const MCRegisterInfo *MRI = nullptr) const;
/// \brief Return the scheduling class for this instruction. The
/// scheduling class is an index into the InstrItineraryData table. This
@@ -572,6 +528,13 @@ public:
}
return -1;
}
private:
/// \brief Return true if this instruction defines the specified physical
/// register, either explicitly or implicitly.
bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
const MCRegisterInfo &RI) const;
};
} // end namespace llvm