Added support for SELECT v8i8 v4i16 for X86 (MMX)

Added support for TRUNC v8i16 to v8i8 for X86 (MMX)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60916 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2008-12-12 01:25:51 +00:00
parent ab55ebda1c
commit 9e5ecb8f8f
3 changed files with 23 additions and 0 deletions

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@ -3937,6 +3937,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
if (Tmp1.getNode()) Result = Tmp1;
}
break;
case TargetLowering::Expand:
assert(Result.getValueType().isVector() && "must be vector type");
// Unroll the truncate. We should do better.
Result = LegalizeOp(UnrollVectorOp(Result));
}
break;
case Expand:

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@ -650,6 +650,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
}
if (Subtarget->hasSSE1()) {
@ -6960,6 +6967,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
case X86::CMOV_V1I64:
case X86::CMOV_FR32:
case X86::CMOV_FR64:
case X86::CMOV_V4F32:

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@ -681,3 +681,14 @@ def : Pat<(v8i8 (bitconvert (i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))))),
(v8i8 (MMX_MOVDQ2Qrr VR128:$src))>;
// CMOV* - Used to implement the SELECT DAG operation. Expanded by the
// scheduler into a branch sequence.
// These are expanded by the scheduler.
let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
def CMOV_V1I64 : I<0, Pseudo,
(outs VR64:$dst), (ins VR64:$t, VR64:$f, i8imm:$cond),
"#CMOV_V1I64 PSEUDO!",
[(set VR64:$dst,
(v1i64 (X86cmov VR64:$t, VR64:$f, imm:$cond,
EFLAGS)))]>;
}