From 9e639e8fd95488cb4c8ef2f7f3a41919acb29ac4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 11 Jul 2013 16:22:38 +0000 Subject: [PATCH] Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186098 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 2 +- include/llvm/CodeGen/LiveVariables.h | 4 ++-- lib/Analysis/CostModel.cpp | 2 +- lib/Analysis/ScalarEvolution.cpp | 2 +- lib/Analysis/ValueTracking.cpp | 2 +- lib/Bitcode/Reader/BitcodeReader.h | 10 +++++----- lib/Bitcode/Writer/BitcodeWriter.cpp | 14 +++++++------- lib/Bitcode/Writer/ValueEnumerator.h | 2 +- lib/CodeGen/LiveInterval.cpp | 2 +- lib/CodeGen/LiveVariables.cpp | 4 ++-- lib/CodeGen/MachineLICM.cpp | 8 ++++---- 11 files changed, 26 insertions(+), 26 deletions(-) diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index cb09a496663..efad0c65fe8 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -389,7 +389,7 @@ namespace llvm { void join(LiveInterval &Other, const int *ValNoAssignments, const int *RHSValNoAssignments, - SmallVector &NewVNInfo, + SmallVectorImpl &NewVNInfo, MachineRegisterInfo *MRI); /// isInOneLiveRange - Return true if the range specified is entirely in the diff --git a/include/llvm/CodeGen/LiveVariables.h b/include/llvm/CodeGen/LiveVariables.h index 6628fd278e4..dc735f7b50b 100644 --- a/include/llvm/CodeGen/LiveVariables.h +++ b/include/llvm/CodeGen/LiveVariables.h @@ -157,8 +157,8 @@ private: // Intermediate data structures void HandlePhysRegUse(unsigned Reg, MachineInstr *MI); void HandlePhysRegDef(unsigned Reg, MachineInstr *MI, - SmallVector &Defs); - void UpdatePhysRegDefs(MachineInstr *MI, SmallVector &Defs); + SmallVectorImpl &Defs); + void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl &Defs); /// FindLastRefOrPartRef - Return the last reference or partial reference of /// the specified register. diff --git a/lib/Analysis/CostModel.cpp b/lib/Analysis/CostModel.cpp index 307795c6f5a..927508e0a7f 100644 --- a/lib/Analysis/CostModel.cpp +++ b/lib/Analysis/CostModel.cpp @@ -81,7 +81,7 @@ CostModelAnalysis::runOnFunction(Function &F) { return false; } -static bool isReverseVectorMask(SmallVector &Mask) { +static bool isReverseVectorMask(SmallVectorImpl &Mask) { for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i) if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i)) return false; diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp index 1d5e5fb7195..69beaafbe0f 100644 --- a/lib/Analysis/ScalarEvolution.cpp +++ b/lib/Analysis/ScalarEvolution.cpp @@ -1380,7 +1380,7 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op, /// static bool CollectAddOperandsWithScales(DenseMap &M, - SmallVector &NewOps, + SmallVectorImpl &NewOps, APInt &AccumulatedConstant, const SCEV *const *Ops, size_t NumOperands, const APInt &Scale, diff --git a/lib/Analysis/ValueTracking.cpp b/lib/Analysis/ValueTracking.cpp index 1b20a25ef26..84a6346f759 100644 --- a/lib/Analysis/ValueTracking.cpp +++ b/lib/Analysis/ValueTracking.cpp @@ -1526,7 +1526,7 @@ Value *llvm::isBytewiseValue(Value *V) { // struct. To is the result struct built so far, new insertvalue instructions // build on that. static Value *BuildSubAggregate(Value *From, Value* To, Type *IndexedType, - SmallVector &Idxs, + SmallVectorImpl &Idxs, unsigned IdxSkip, Instruction *InsertBefore) { llvm::StructType *STy = dyn_cast(IndexedType); diff --git a/lib/Bitcode/Reader/BitcodeReader.h b/lib/Bitcode/Reader/BitcodeReader.h index 28674eb14ef..e4de4ab7c7c 100644 --- a/lib/Bitcode/Reader/BitcodeReader.h +++ b/lib/Bitcode/Reader/BitcodeReader.h @@ -258,7 +258,7 @@ private: /// getValueTypePair - Read a value/type pair out of the specified record from /// slot 'Slot'. Increment Slot past the number of slots used in the record. /// Return true on failure. - bool getValueTypePair(SmallVector &Record, unsigned &Slot, + bool getValueTypePair(SmallVectorImpl &Record, unsigned &Slot, unsigned InstNum, Value *&ResVal) { if (Slot == Record.size()) return true; unsigned ValNo = (unsigned)Record[Slot++]; @@ -282,7 +282,7 @@ private: /// popValue - Read a value out of the specified record from slot 'Slot'. /// Increment Slot past the number of slots used by the value in the record. /// Return true if there is an error. - bool popValue(SmallVector &Record, unsigned &Slot, + bool popValue(SmallVectorImpl &Record, unsigned &Slot, unsigned InstNum, Type *Ty, Value *&ResVal) { if (getValue(Record, Slot, InstNum, Ty, ResVal)) return true; @@ -292,7 +292,7 @@ private: } /// getValue -- Like popValue, but does not increment the Slot number. - bool getValue(SmallVector &Record, unsigned Slot, + bool getValue(SmallVectorImpl &Record, unsigned Slot, unsigned InstNum, Type *Ty, Value *&ResVal) { ResVal = getValue(Record, Slot, InstNum, Ty); return ResVal == 0; @@ -300,7 +300,7 @@ private: /// getValue -- Version of getValue that returns ResVal directly, /// or 0 if there is an error. - Value *getValue(SmallVector &Record, unsigned Slot, + Value *getValue(SmallVectorImpl &Record, unsigned Slot, unsigned InstNum, Type *Ty) { if (Slot == Record.size()) return 0; unsigned ValNo = (unsigned)Record[Slot]; @@ -311,7 +311,7 @@ private: } /// getValueSigned -- Like getValue, but decodes signed VBRs. - Value *getValueSigned(SmallVector &Record, unsigned Slot, + Value *getValueSigned(SmallVectorImpl &Record, unsigned Slot, unsigned InstNum, Type *Ty) { if (Slot == Record.size()) return 0; unsigned ValNo = (unsigned)decodeSignRotatedValue(Record[Slot]); diff --git a/lib/Bitcode/Writer/BitcodeWriter.cpp b/lib/Bitcode/Writer/BitcodeWriter.cpp index 1b73f23e8f6..08b72a46913 100644 --- a/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -614,7 +614,7 @@ static uint64_t GetOptimizationFlags(const Value *V) { static void WriteMDNode(const MDNode *N, const ValueEnumerator &VE, BitstreamWriter &Stream, - SmallVector &Record) { + SmallVectorImpl &Record) { for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { if (N->getOperand(i)) { Record.push_back(VE.getTypeID(N->getOperand(i)->getType())); @@ -701,7 +701,7 @@ static void WriteFunctionLocalMetadata(const Function &F, BitstreamWriter &Stream) { bool StartedMetadataBlock = false; SmallVector Record; - const SmallVector &Vals = VE.getFunctionLocalMDValues(); + const SmallVectorImpl &Vals = VE.getFunctionLocalMDValues(); for (unsigned i = 0, e = Vals.size(); i != e; ++i) if (const MDNode *N = Vals[i]) if (N->isFunctionLocal() && N->getFunction() == &F) { @@ -1078,7 +1078,7 @@ static void WriteModuleConstants(const ValueEnumerator &VE, /// instruction ID, then it is a forward reference, and it also includes the /// type ID. The value ID that is written is encoded relative to the InstID. static bool PushValueAndType(const Value *V, unsigned InstID, - SmallVector &Vals, + SmallVectorImpl &Vals, ValueEnumerator &VE) { unsigned ValID = VE.getValueID(V); // Make encoding relative to the InstID. @@ -1093,21 +1093,21 @@ static bool PushValueAndType(const Value *V, unsigned InstID, /// pushValue - Like PushValueAndType, but where the type of the value is /// omitted (perhaps it was already encoded in an earlier operand). static void pushValue(const Value *V, unsigned InstID, - SmallVector &Vals, + SmallVectorImpl &Vals, ValueEnumerator &VE) { unsigned ValID = VE.getValueID(V); Vals.push_back(InstID - ValID); } static void pushValue64(const Value *V, unsigned InstID, - SmallVector &Vals, + SmallVectorImpl &Vals, ValueEnumerator &VE) { uint64_t ValID = VE.getValueID(V); Vals.push_back(InstID - ValID); } static void pushValueSigned(const Value *V, unsigned InstID, - SmallVector &Vals, + SmallVectorImpl &Vals, ValueEnumerator &VE) { unsigned ValID = VE.getValueID(V); int64_t diff = ((int32_t)InstID - (int32_t)ValID); @@ -1117,7 +1117,7 @@ static void pushValueSigned(const Value *V, unsigned InstID, /// WriteInstruction - Emit an instruction to the specified stream. static void WriteInstruction(const Instruction &I, unsigned InstID, ValueEnumerator &VE, BitstreamWriter &Stream, - SmallVector &Vals) { + SmallVectorImpl &Vals) { unsigned Code = 0; unsigned AbbrevToUse = 0; VE.setInstructionID(&I); diff --git a/lib/Bitcode/Writer/ValueEnumerator.h b/lib/Bitcode/Writer/ValueEnumerator.h index 0af6164c944..d1ca15f45d0 100644 --- a/lib/Bitcode/Writer/ValueEnumerator.h +++ b/lib/Bitcode/Writer/ValueEnumerator.h @@ -125,7 +125,7 @@ public: const ValueList &getValues() const { return Values; } const ValueList &getMDValues() const { return MDValues; } - const SmallVector &getFunctionLocalMDValues() const { + const SmallVectorImpl &getFunctionLocalMDValues() const { return FunctionLocalMDs; } const TypeList &getTypes() const { return Types; } diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index 861e99b785d..6be6bf3688a 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -415,7 +415,7 @@ void LiveInterval::removeValNo(VNInfo *ValNo) { void LiveInterval::join(LiveInterval &Other, const int *LHSValNoAssignments, const int *RHSValNoAssignments, - SmallVector &NewVNInfo, + SmallVectorImpl &NewVNInfo, MachineRegisterInfo *MRI) { verify(); diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 6f75700f130..ed55d7ad10b 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -441,7 +441,7 @@ void LiveVariables::HandleRegMask(const MachineOperand &MO) { } void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, - SmallVector &Defs) { + SmallVectorImpl &Defs) { // What parts of the register are previously defined? SmallSet Live; if (PhysRegDef[Reg] || PhysRegUse[Reg]) { @@ -484,7 +484,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI, } void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI, - SmallVector &Defs) { + SmallVectorImpl &Defs) { while (!Defs.empty()) { unsigned Reg = Defs.back(); Defs.pop_back(); diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index ed3ed4d4d91..6ad4e392adf 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -172,7 +172,7 @@ namespace { BitVector &PhysRegDefs, BitVector &PhysRegClobbers, SmallSet &StoredFIs, - SmallVector &Candidates); + SmallVectorImpl &Candidates); /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the /// current loop. @@ -404,7 +404,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, BitVector &PhysRegClobbers, SmallSet &StoredFIs, - SmallVector &Candidates) { + SmallVectorImpl &Candidates) { bool RuledOut = false; bool HasNonInvariantUse = false; unsigned Def = 0; @@ -1084,7 +1084,7 @@ bool MachineLICM::CanCauseHighRegPressure(DenseMap &Cost, return true; for (unsigned i = BackTrace.size(); i != 0; --i) { - SmallVector &RP = BackTrace[i-1]; + SmallVectorImpl &RP = BackTrace[i-1]; if (RP[RCId] + Cost >= Limit) return true; } @@ -1130,7 +1130,7 @@ void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) { // Update register pressure of blocks from loop header to current block. for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) { - SmallVector &RP = BackTrace[i]; + SmallVectorImpl &RP = BackTrace[i]; for (DenseMap::iterator CI = Cost.begin(), CE = Cost.end(); CI != CE; ++CI) { unsigned RCId = CI->first;