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[Hexagon] Adding round reg/imm and bitsplit instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225188 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3220,6 +3220,13 @@ class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
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let Inst{7-5} = MinOp;
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let Inst{4-0} = dst;
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}
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class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
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: T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
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let hasNewValue = 1 in
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class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
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: T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
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let hasNewValue = 1 in
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class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
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@ -1747,6 +1747,20 @@ def M4_xor_xacc
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let Inst{12-8} = Rtt;
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let Inst{4-0} = Rxx;
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}
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// Split bitfield
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let isCodeGenOnly = 0 in
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def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
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// Arithmetic/Convergent round
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let isCodeGenOnly = 0 in
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def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
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let isCodeGenOnly = 0 in
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def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>;
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let Defs = [USR_OVF], isCodeGenOnly = 0 in
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def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
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// Add and accumulate.
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// Rd=add(Rs,add(Ru,#s6))
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@ -86,6 +86,12 @@
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# CHECK: r17:16 = neg(r21:20)
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0xd1 0xc0 0x95 0x8c
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# CHECK: r17 = neg(r21):sat
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0x11 0xdf 0xf5 0x8c
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# CHECK: r17 = cround(r21, #31)
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0x91 0xdf 0xf5 0x8c
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# CHECK: r17 = round(r21, #31)
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0xd1 0xdf 0xf5 0x8c
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# CHECK: r17 = round(r21, #31):sat
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0x71 0xd5 0x1f 0xef
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# CHECK: r17 += sub(r21, r31)
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0x11 0xd5 0x3f 0xd5
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@ -64,6 +64,8 @@
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# CHECK: r17 = clrbit(r21, r31)
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0x91 0xdf 0x95 0xc6
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# CHECK: r17 = togglebit(r21, r31)
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0x90 0xdf 0xd5 0x88
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# CHECK: r17:16 = bitsplit(r21, #31)
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0xf1 0xcd 0x15 0x87
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# CHECK: r17 = tableidxb(r21, #7, #13):raw
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0xf1 0xcd 0x55 0x87
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