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The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2108,18 +2108,25 @@ bool ARMFastISel::SelectCall(const Instruction *I,
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MachineInstrBuilder MIB;
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unsigned CallOpc = ARMSelectCallOp(GV);
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// Explicitly adding the predicate here.
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if(isThumb2)
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if(isThumb2) {
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// Explicitly adding the predicate here.
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc)));
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else
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// Explicitly adding the predicate here.
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc)));
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if (!IntrMemName)
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MIB.addGlobalAddress(GV, 0, 0);
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else
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MIB.addExternalSymbol(IntrMemName, 0);
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if (!IntrMemName)
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MIB.addGlobalAddress(GV, 0, 0);
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else
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MIB.addExternalSymbol(IntrMemName, 0);
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} else {
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if (!IntrMemName)
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// Explicitly adding the predicate here.
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc))
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.addGlobalAddress(GV, 0, 0));
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else
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc))
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.addExternalSymbol(IntrMemName, 0));
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}
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// Add implicit physical register uses to the call.
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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@ -2136,7 +2143,6 @@ bool ARMFastISel::SelectCall(const Instruction *I,
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}
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bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
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if (!isThumb2) return false;
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// FIXME: Handle more intrinsics.
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switch (I.getIntrinsicID()) {
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default: return false;
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@ -1,3 +1,4 @@
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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@message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
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@ -10,7 +11,7 @@ define void @t1() nounwind ssp {
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; ARM: movw r1, #64
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; ARM: movw r2, #10
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; ARM: uxtb r1, r1
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; ARM: bl #14
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; ARM: bl _memset
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; THUMB: t1
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; THUMB: ldr.n r0, LCPI0_0
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; THUMB: adds r0, #5
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@ -36,7 +37,7 @@ define void @t2() nounwind ssp {
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; ARM: str r0, [sp] @ 4-byte Spill
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; ARM: mov r0, r1
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; ARM: ldr r1, [sp] @ 4-byte Reload
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; ARM: bl #14
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; ARM: bl _memcpy
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; THUMB: t2
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; THUMB: ldr.n r0, LCPI1_0
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; THUMB: ldr r0, [r0]
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@ -60,7 +61,7 @@ define void @t3() nounwind ssp {
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; ARM: add r0, r0, #16
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; ARM: movw r2, #10
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; ARM: mov r0, r1
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; ARM: bl #14
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; ARM: bl _memmove
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; THUMB: t3
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; THUMB: ldr.n r0, LCPI2_0
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; THUMB: ldr r0, [r0]
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