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https://github.com/c64scene-ar/llvm-6502.git
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Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
8783e401a3
commit
9ef4835bd8
@ -151,6 +151,18 @@ private:
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/// SelectCMOVOp - Select CMOV instructions for ARM.
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SDNode *SelectCMOVOp(SDValue Op);
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SDNode *SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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SDNode *SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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@ -1305,15 +1317,92 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::
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SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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SDValue CPTmp0;
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SDValue CPTmp1;
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if (SelectT2ShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1)) {
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unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
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unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
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unsigned Opc = 0;
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switch (SOShOp) {
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case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
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case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
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case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
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case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
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default:
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llvm_unreachable("Unknown so_reg opcode!");
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break;
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}
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SDValue SOShImm =
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CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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SDValue CPTmp0;
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (SelectShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (!T)
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return 0;
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if (Predicate_t2_so_imm(TrueVal.getNode())) {
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SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::t2MOVCCi, MVT::i32, Ops, 5);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::
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SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
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ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
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ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
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if (!T)
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return 0;
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if (Predicate_so_imm(TrueVal.getNode())) {
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SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
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SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCi, MVT::i32, Ops, 5);
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}
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return 0;
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}
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SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
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EVT VT = Op.getValueType();
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SDValue N0 = Op.getOperand(0);
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SDValue N1 = Op.getOperand(1);
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SDValue N2 = Op.getOperand(2);
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SDValue N3 = Op.getOperand(3);
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SDValue FalseVal = Op.getOperand(0);
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SDValue TrueVal = Op.getOperand(1);
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SDValue CC = Op.getOperand(2);
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SDValue CCR = Op.getOperand(3);
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SDValue InFlag = Op.getOperand(4);
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assert(N2.getOpcode() == ISD::Constant);
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assert(N3.getOpcode() == ISD::Register);
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assert(CC.getOpcode() == ISD::Constant);
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assert(CCR.getOpcode() == ISD::Register);
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ARMCC::CondCodes CCVal =
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(ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
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if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
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// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
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@ -1323,36 +1412,21 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
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SDValue CPTmp1;
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SDValue CPTmp2;
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if (Subtarget->isThumb()) {
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if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
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unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
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unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
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unsigned Opc = 0;
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switch (SOShOp) {
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case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
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case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
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case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
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case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
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default:
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llvm_unreachable("Unknown so_reg opcode!");
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break;
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}
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SDValue SOShImm =
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CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
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}
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SDNode *Res = SelectT2CMOVShiftOp(Op, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectT2CMOVShiftOp(Op, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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} else {
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if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCs, MVT::i32, Ops, 7);
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}
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SDNode *Res = SelectARMCMOVShiftOp(Op, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectARMCMOVShiftOp(Op, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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}
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// Pattern: (ARMcmov:i32 GPR:i32:$false,
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@ -1361,32 +1435,22 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
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// Emits: (MOVCCi:i32 GPR:i32:$false,
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// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
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// Pattern complexity = 10 cost = 1 size = 0
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if (N3.getOpcode() == ISD::Constant) {
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if (Subtarget->isThumb()) {
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if (Predicate_t2_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::t2MOVCCi, MVT::i32, Ops, 5);
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}
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} else {
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if (Predicate_so_imm(N3.getNode())) {
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SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N1)->getZExtValue()),
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MVT::i32);
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
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return CurDAG->SelectNodeTo(Op.getNode(),
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ARM::MOVCCi, MVT::i32, Ops, 5);
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}
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}
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if (Subtarget->isThumb()) {
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SDNode *Res = SelectT2CMOVSoImmOp(Op, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectT2CMOVSoImmOp(Op, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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} else {
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SDNode *Res = SelectARMCMOVSoImmOp(Op, FalseVal, TrueVal,
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CCVal, CCR, InFlag);
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if (!Res)
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Res = SelectARMCMOVSoImmOp(Op, TrueVal, FalseVal,
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ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
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if (Res)
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return Res;
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}
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}
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@ -1399,10 +1463,8 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
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// Pattern complexity = 6 cost = 11 size = 0
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//
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// Also FCPYScc and FCPYDcc.
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SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
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cast<ConstantSDNode>(N2)->getZExtValue()),
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MVT::i32);
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SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
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SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
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SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
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unsigned Opc = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: assert(false && "Illegal conditional move type!");
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@ -1,5 +1,5 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin
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; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5
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; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3
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%struct.CONTENTBOX = type { i32, i32, i32, i32, i32 }
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%struct.LOCBOX = type { i32, i32, i32, i32 }
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48
test/CodeGen/ARM/select-imm.ll
Normal file
48
test/CodeGen/ARM/select-imm.ll
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@ -0,0 +1,48 @@
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; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2
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define arm_apcscc i32 @t1(i32 %c) nounwind readnone {
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entry:
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; ARM: t1:
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; ARM: mov r1, #101
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; ARM: orr r1, r1, #1, 24
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; ARM: movgt r0, #123
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; T2: t1:
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; T2: movw r0, #357
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; T2: movgt r0, #123
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%0 = icmp sgt i32 %c, 1
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%1 = select i1 %0, i32 123, i32 357
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ret i32 %1
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}
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define arm_apcscc i32 @t2(i32 %c) nounwind readnone {
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entry:
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; ARM: t2:
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; ARM: mov r1, #101
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; ARM: orr r1, r1, #1, 24
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; ARM: movle r0, #123
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; T2: t2:
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; T2: movw r0, #357
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; T2: movle r0, #123
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%0 = icmp sgt i32 %c, 1
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%1 = select i1 %0, i32 357, i32 123
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ret i32 %1
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}
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define arm_apcscc i32 @t3(i32 %a) nounwind readnone {
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entry:
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; ARM: t3:
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; ARM: mov r0, #0
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; ARM: moveq r0, #1
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; T2: t3:
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; T2: mov r0, #0
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; T2: moveq r0, #1
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%0 = icmp eq i32 %a, 160
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%1 = zext i1 %0 to i32
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ret i32 %1
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}
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