6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-02 07:11:49 +00:00
Code Issues Projects Releases Wiki Activity

[mips][msa] Implemented fill.d intrinsic.

Browse Source 
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-09-27 13:20:41 +00:00
parent e8eafdb676
commit 9f30d43122
3 changed files with 40 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/IR/IntrinsicsMips.td
View File

@ -983,6 +983,8 @@ def int_mips_fill_h : GCCBuiltin<"__builtin_msa_fill_h">,
Intrinsic<[llvm_v8i16_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_mips_fill_w : GCCBuiltin<"__builtin_msa_fill_w">,
Intrinsic<[llvm_v4i32_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_mips_fill_d : GCCBuiltin<"__builtin_msa_fill_d">,
Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty], [IntrNoMem]>;
def int_mips_flog2_w : GCCBuiltin<"__builtin_msa_flog2_w">,
Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;

8
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -1325,15 +1325,17 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
Op->getOperand(2));
case Intrinsic::mips_fill_b:
case Intrinsic::mips_fill_h:
case Intrinsic::mips_fill_w: {
case Intrinsic::mips_fill_w:
case Intrinsic::mips_fill_d: {
SmallVector<SDValue, 16> Ops;
EVT ResTy = Op->getValueType(0);
for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
Ops.push_back(Op->getOperand(1));
return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0],
Ops.size());
// If ResTy is v2i64 then the type legalizer will break this node down into
// an equivalent v4i32.
return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
}
case Intrinsic::mips_flog2_w:
case Intrinsic::mips_flog2_d:

42
test/CodeGen/Mips/msa/2r_vector_scalar.ll
View File

@ -17,9 +17,9 @@ entry:
declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
; CHECK: llvm_mips_fill_b_test:
; CHECK: lw
; CHECK: fill.b
; CHECK: st.b
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.b [[R2]],
; CHECK: .size llvm_mips_fill_b_test
;
@llvm_mips_fill_h_ARG1 = global i32 23, align 16
@ -36,9 +36,9 @@ entry:
declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
; CHECK: llvm_mips_fill_h_test:
; CHECK: lw
; CHECK: fill.h
; CHECK: st.h
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.h [[R2]],
; CHECK: .size llvm_mips_fill_h_test
;
@llvm_mips_fill_w_ARG1 = global i32 23, align 16
@ -55,8 +55,32 @@ entry:
declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
; CHECK: llvm_mips_fill_w_test:
; CHECK: lw
; CHECK: fill.w
; CHECK: st.w
; CHECK-DAG: lw [[R1:\$[0-9]+]],
; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
; CHECK-DAG: st.w [[R2]],
; CHECK: .size llvm_mips_fill_w_test
;
@llvm_mips_fill_d_ARG1 = global i64 23, align 16
@llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_fill_d_test() nounwind {
entry:
%0 = load i64* @llvm_mips_fill_d_ARG1
%1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
ret void
}
declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
; CHECK: llvm_mips_fill_d_test:
; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0
; CHECK-DAG: insert.w [[R3]][0], [[R1]]
; CHECK-DAG: insert.w [[R3]][1], [[R2]]
; CHECK-DAG: insert.w [[R3]][2], [[R1]]
; CHECK-DAG: insert.w [[R3]][3], [[R2]]
; CHECK-DAG: st.w [[R3]],
; CHECK: .size llvm_mips_fill_d_test
;