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[Hexagon] Adding JR class predicated call reg instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223933 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-10 18:24:16 +00:00
parent 4912640253
commit 9f3b3bca89
3 changed files with 42 additions and 0 deletions
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28
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1383,6 +1383,34 @@ multiclass JMPR_base<string BaseOp> {
}
}
let isCall = 1, hasSideEffects = 1 in
class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
dag InputDag = (ins IntRegs:$Rs)>
: JRInst<(outs), InputDag,
!if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
"if ($Pu) callr $Rs"),
"callr $Rs"),
[], "", J_tc_2early_SLOT2> {
bits<5> Rs;
bits<2> Pu;
let isPredicated = isPred;
let isPredicatedFalse = isPredNot;
let IClass = 0b0101;
let Inst{27-25} = 0b000;
let Inst{24-23} = !if (isPred, 0b10, 0b01);
let Inst{22} = 0;
let Inst{21} = isPredNot;
let Inst{9-8} = !if (isPred, Pu, 0b00);
let Inst{20-16} = Rs;
}
let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>;
def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
}
let isTerminator = 1, hasSideEffects = 0 in {
let isBranch = 1 in
defm JMP : JMP_base<"JMP">, PredNewRel;

8
lib/Target/Hexagon/HexagonRegisterInfo.td
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@ -145,6 +145,14 @@ def CRRegs : RegisterClass<"Hexagon", [i32], 32,
let Size = 32;
}
def VolatileV3 {
list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
R28, R31,
P0, P1, P2, P3,
M0, M1,
LC0, LC1, SA0, SA1, USR_OVF];
}
def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
[{
return isPositiveHalfWord(N);

6
test/MC/Disassembler/Hexagon/jr.txt Normal file
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@ -0,0 +1,6 @@
# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
0x00 0xc1 0x15 0x51
# CHECK: if (p1) callr r21
0x00 0xc3 0x35 0x51
# CHECK: if (!p3) callr r21