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Address a FIXME and update the fast unaligned memory feature for newer

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Intel chips.

The model number rules were determined by inspecting Intel's
documentation for their newer chip model numbers. My understanding is
that all of the newer Intel chips have fast unaligned memory access, but
if anyone is concerned about a particular chip, just shout.

No tests updated; it's not clear we have dedicated tests for the chips'
various features, but if anyone would like tests (or can point me at
some existing ones), I'm happy to oblige.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2012-12-10 09:18:44 +00:00
parent ed90ed077a
commit 9f3f40f6ef
2 changed files with 21 additions and 13 deletions
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14
lib/Target/X86/X86.td
View File

@ -182,17 +182,17 @@ def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
// Sandy Bridge // Sandy Bridge
// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
// rather than a superset. // rather than a superset.
def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
FeatureAES, FeaturePCLMUL]>; FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
// Ivy Bridge // Ivy Bridge
def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT, def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
FeatureAES, FeaturePCLMUL, FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>; FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
// Haswell // Haswell
def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT, def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
FeatureF16C, FeatureFSGSBase, FeatureRDRAND, FeatureF16C, FeatureFSGSBase,
FeatureMOVBE, FeatureLZCNT, FeatureBMI, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
FeatureBMI2, FeatureFMA, FeatureBMI2, FeatureFMA,
FeatureRTM]>; FeatureRTM]>;

20
lib/Target/X86/X86Subtarget.cpp
View File

@ -234,12 +234,20 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
ToggleFeature(X86::FeatureSlowBTMem); ToggleFeature(X86::FeatureSlowBTMem);
} }
// If it's Nehalem, unaligned memory access is fast. // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
// Include Westmere and Sandy Bridge as well. // memory access is fast. We hard code model numbers here because they
// FIXME: add later processors. // aren't strictly increasing for Intel chips it seems.
if (IsIntel && ((Family == 6 && Model == 26) || if (IsIntel &&
(Family == 6 && Model == 44) || ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
(Family == 6 && Model == 42))) { // Jasper Froest
(Family == 6 && Model == 0x2A) || // Nehalem: Bloomfield, Nehalem-EP
(Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
(Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
(Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
(Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
(Family == 6 && Model == 0x2A) || // SandyBridge
(Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
(Family == 6 && Model == 0x3A))) {// IvyBridge
IsUAMemFast = true; IsUAMemFast = true;
ToggleFeature(X86::FeatureFastUAMem); ToggleFeature(X86::FeatureFastUAMem);
} }