6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-27 13:30:05 +00:00
Code Issues Projects Releases Wiki Activity

Support for microMIPS trap instructions 1.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2013-11-07 14:35:24 +00:00
parent 0f0f1ac011
commit 9f471750fa
6 changed files with 68 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -275,3 +275,18 @@ class BGEZAL_FM_MM<bits<5> funct> : MMArch {
let Inst{20-16} = rs;
let Inst{15-0} = offset;
}
class TEQ_FM_MM<bits<6> funct> : MMArch {
bits<5> rs;
bits<5> rt;
bits<4> code_;
bits<32> Inst;
let Inst{31-26} = 0x00;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-12} = code_;
let Inst{11-6} = funct;
let Inst{5-0} = 0x3c;
}

8
lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -201,4 +201,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
BGEZAL_FM_MM<0x03>;
def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
BGEZAL_FM_MM<0x01>;
/// Trap Instructions
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
}

2
lib/Target/Mips/MipsInstrFormats.td
View File

@ -454,7 +454,7 @@ class RDHWR_FM {
let Inst{5-0} = 0x3b;
}
class TEQ_FM<bits<6> funct> {
class TEQ_FM<bits<6> funct> : StdArch {
bits<5> rs;
bits<5> rt;
bits<10> code_;

15
lib/Target/Mips/MipsInstrInfo.td
View File

@ -658,7 +658,8 @@ class SYNC_FT :
let hasSideEffects = 1 in
class TEQ_FT<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
!strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
!strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
FrmI, opstr>;
class TEQI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
@ -963,12 +964,12 @@ def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
def SYNC : SYNC_FT, SYNC_FM;
def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;

18
test/MC/Disassembler/Mips/micromips.txt
View File

@ -249,3 +249,21 @@
# CHECK: bltz $6, 1332
0x40 0x06 0x02 0x9a
# CHECK: teq $8, $9, 0
0x01 0x28 0x00 0x3c
# CHECK: tge $8, $9, 0
0x01 0x28 0x02 0x3c
# CHECK: tgeu $8, $9, 0
0x01 0x28 0x04 0x3c
# CHECK: tlt $8, $9, 0
0x01 0x28 0x08 0x3c
# CHECK: tltu $8, $9, 0
0x01 0x28 0x0a 0x3c
# CHECK: tne $8, $9, 0
0x01 0x28 0x0c 0x3c

18
test/MC/Disassembler/Mips/micromips_le.txt
View File

@ -249,3 +249,21 @@
# CHECK: bltz $6, 1332
0x06 0x40 0x9a 0x02
# CHECK: teq $8, $9, 0
0x28 0x01 0x3c 0x00
# CHECK: tge $8, $9, 0
0x28 0x01 0x3c 0x02
# CHECK: tgeu $8, $9, 0
0x28 0x01 0x3c 0x04
# CHECK: tlt $8, $9, 0
0x28 0x01 0x3c 0x08
# CHECK: tltu $8, $9, 0
0x28 0x01 0x3c 0x0a
# CHECK: tne $8, $9, 0
0x28 0x01 0x3c 0x0c