From 9f52f2838d99774d3262bfce7b22d70a7a3f0196 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Wed, 31 Aug 2005 00:43:08 +0000 Subject: [PATCH] Fix a mistake in my previous patch pointed out by sabre; the AssertZext case in MaskedValueIsZero was wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23165 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index c550e68e830..aeacfd56884 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1095,10 +1095,11 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, SrcBits = MVT::getSizeInBits(cast(Op.getOperand(3))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::ZERO_EXTEND: - case ISD::AssertZext: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); - + case ISD::AssertZext: + SrcBits = MVT::getSizeInBits(cast(Op.getOperand(1))->getVT()); + return (Mask & ((1ULL << SrcBits)-1) == 0; // Returning only the zext bits. case ISD::AND: // (X & C1) & C2 == 0 iff C1 & C2 == 0. if (ConstantSDNode *AndRHS = dyn_cast(Op.getOperand(1)))