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Generate the fchs instruction to negate a floating point number

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11078 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-02-02 19:31:38 +00:00
parent 4a06f35484
commit 9f8fd6d9ea
3 changed files with 22 additions and 2 deletions
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8
lib/Target/X86/InstSelectSimple.cpp
View File

@@ -1227,7 +1227,13 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
return; return;
} }
} }
} } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
if (CFP->isExactlyValue(-0.0)) {
// -0.0 - X === -X
unsigned op1Reg = getReg(Op1, MBB, IP);
BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
return;
}
if (!isa<ConstantInt>(Op1) || Class == cLong) { if (!isa<ConstantInt>(Op1) || Class == cLong) {
static const unsigned OpcodeTab[][4] = { static const unsigned OpcodeTab[][4] = {

8
lib/Target/X86/X86ISelSimple.cpp
View File

@@ -1227,7 +1227,13 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
return; return;
} }
} }
} } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
if (CFP->isExactlyValue(-0.0)) {
// -0.0 - X === -X
unsigned op1Reg = getReg(Op1, MBB, IP);
BMI(MBB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
return;
}
if (!isa<ConstantInt>(Op1) || Class == cLong) { if (!isa<ConstantInt>(Op1) || Class == cLong) {
static const unsigned OpcodeTab[][4] = { static const unsigned OpcodeTab[][4] = {

8
lib/Target/X86/X86InstrInfo.td
View File

@@ -388,6 +388,10 @@ def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB; // R32 = z
class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp> class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
: X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; } : X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
// Pseudo instructions for floating point. We use these pseudo instructions
// because they can be expanded by the fp spackifier into one of many different
// forms of instructions for doing these operations. Until the stackifier runs,
// we prefer to be abstract.
def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
@@ -429,6 +433,10 @@ def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fx
def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9; def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9; def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
// Unary read-modify-write operations...
def FCHS : FPInst<"fchs", 0xE0, RawFrm, ArgF80, OneArgFPRW>, D9, Imp<[ST0],[ST0]>; // f1 = fchs f2
// Binary arithmetic operations... // Binary arithmetic operations...
class FPST0rInst<string n, bits<8> o> class FPST0rInst<string n, bits<8> o>
: X86Inst<n, o, AddRegFrm, ArgF80>, D8 { : X86Inst<n, o, AddRegFrm, ArgF80>, D8 {