From a007781bdf0e9147165d3b2e5aa21e58c3b7c8b0 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 29 Oct 2010 18:41:40 +0000 Subject: [PATCH] Convert this file to less fragile .s form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117681 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/neon-bitcount-encoding.ll | 118 -------------------------- test/MC/ARM/neon-bitcount-encoding.s | 32 +++++++ 2 files changed, 32 insertions(+), 118 deletions(-) delete mode 100644 test/MC/ARM/neon-bitcount-encoding.ll create mode 100644 test/MC/ARM/neon-bitcount-encoding.s diff --git a/test/MC/ARM/neon-bitcount-encoding.ll b/test/MC/ARM/neon-bitcount-encoding.ll deleted file mode 100644 index 7f117f1db94..00000000000 --- a/test/MC/ARM/neon-bitcount-encoding.ll +++ /dev/null @@ -1,118 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] - %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1) - ret <8 x i8> %tmp2 -} - -define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3] - %tmp2 = call <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8> %tmp1) - ret <16 x i8> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone -declare <16 x i8> @llvm.arm.neon.vcnt.v16i8(<16 x i8>) nounwind readnone - -define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3] - %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1) - ret <8 x i8> %tmp2 -} - -define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3] - %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1) - ret <4 x i16> %tmp2 -} - -define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3] - %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1) - ret <2 x i32> %tmp2 -} - -define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3] - %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1) - ret <16 x i8> %tmp2 -} - -define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1) - ret <8 x i16> %tmp2 -} - -define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32> %tmp1) - ret <4 x i32> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vclz.v4i32(<4 x i32>) nounwind readnone - -define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3] - %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) - ret <8 x i8> %tmp2 -} - -define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3] - %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) - ret <4 x i16> %tmp2 -} - -define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3] - %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) - ret <2 x i32> %tmp2 -} - -define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3] - %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) - ret <16 x i8> %tmp2 -} - -define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) - ret <8 x i16> %tmp2 -} - -define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) - ret <4 x i32> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32>) nounwind readnone diff --git a/test/MC/ARM/neon-bitcount-encoding.s b/test/MC/ARM/neon-bitcount-encoding.s new file mode 100644 index 00000000000..1693711f8ea --- /dev/null +++ b/test/MC/ARM/neon-bitcount-encoding.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s +// XFAIL: * + +// CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] + vcnt.8 d16, d16 +// CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xf3] + vcnt.8 q8, q8 +// CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3] + vclz.i8 d16, d16 +// CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3] + vclz.i16 d16, d16 +// CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3] + vclz.i32 d16, d16 +// CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3] + vclz.i8 q8, q8 +// CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3] + vclz.i16 q8, q8 +// CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3] + vclz.i32 q8, q8 +// CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3] + vcls.s8 d16, d16 +// CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3] + vcls.s16 d16, d16 +// CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3] + vcls.s32 d16, d16 +// CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3] + vcls.s8 q8, q8 +// CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3] + vcls.s16 q8, q8 +// CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xf3] + vcls.s32 q8, q8 +