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Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142205 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,6 +28,9 @@ def Subtract32 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getZExtValue() - 32);
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return getI32Imm((unsigned)N->getZExtValue() - 32);
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}]>;
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}]>;
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// shamt field must fit in 5 bits.
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def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
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// imm32_63 predicate - True if imm is in range [32, 63].
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// imm32_63 predicate - True if imm is in range [32, 63].
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def imm32_63 : ImmLeaf<i64,
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def imm32_63 : ImmLeaf<i64,
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[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
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[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
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@ -113,9 +116,9 @@ def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
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def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
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def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
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/// Shift Instructions
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/// Shift Instructions
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def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
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def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5_64>;
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def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
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def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5_64>;
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def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
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def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5_64>;
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def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
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def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
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def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
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def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
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def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
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def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
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@ -125,7 +128,8 @@ def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
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// Rotate Instructions
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// Rotate Instructions
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let Predicates = [HasMips64r2] in {
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let Predicates = [HasMips64r2] in {
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def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
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def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr,
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immZExt5_64>;
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def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
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def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
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imm32_63>;
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imm32_63>;
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def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
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def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
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@ -191,9 +191,7 @@ def immZExt16 : PatLeaf<(imm), [{
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}], LO16>;
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}], LO16>;
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// shamt field must fit in 5 bits.
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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// since load and store instructions from stack used it.
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@ -41,10 +41,10 @@ MipsTargetMachine(const Target &T, StringRef TT,
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Subtarget(TT, CPU, FS, isLittle),
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Subtarget(TT, CPU, FS, isLittle),
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DataLayout(isLittle ?
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DataLayout(isLittle ?
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(Subtarget.isABI_N64() ?
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(Subtarget.isABI_N64() ?
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"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
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"e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
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"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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"e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
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(Subtarget.isABI_N64() ?
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(Subtarget.isABI_N64() ?
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"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
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"E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-n32" :
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"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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"E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
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InstrInfo(*this),
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InstrInfo(*this),
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FrameLowering(Subtarget),
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FrameLowering(Subtarget),
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