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Use BIT_CONVERT to simplify this code

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24975 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-23 02:31:39 +00:00
parent 1b95e0ba92
commit a01874fc89
2 changed files with 22 additions and 72 deletions
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47
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@@ -226,14 +226,8 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MF.addLiveIn(*CurArgReg++, VReg); MF.addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
// We use the stack space that is already reserved for this reg. Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); ArgValues.push_back(Arg);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
Arg, FIPtr, SV);
ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
} }
ArgOffset += 4; ArgOffset += 4;
break; break;
@@ -280,20 +274,12 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// Compose the two halves together into an i64 unit. // Compose the two halves together into an i64 unit.
SDOperand WholeValue = SDOperand WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
if (ObjectVT == MVT::i64) { // If we want a double, do a bit convert.
// If we are emitting an i64, this is what we want. if (ObjectVT == MVT::f64)
ArgValues.push_back(WholeValue); WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
} else {
assert(ObjectVT == MVT::f64); ArgValues.push_back(WholeValue);
// Otherwise, emit a store to the stack and reload into FPR.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
WholeValue, FIPtr, SV);
ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
}
} }
ArgOffset += 8; ArgOffset += 8;
break; break;
@@ -418,16 +404,11 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
ValToStore = Val; ValToStore = Val;
} else { } else {
// Convert this to a FP value in an int reg. // Convert this to a FP value in an int reg.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Val, FIPtr, SV);
Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
RegValuesToPass.push_back(Val); RegValuesToPass.push_back(Val);
} }
break; break;
case MVT::f64: { case MVT::f64:
ObjSize = 8; ObjSize = 8;
// If we can store this directly into the outgoing slot, do so. We can // If we can store this directly into the outgoing slot, do so. We can
// do this when all ArgRegs are used and if the outgoing slot is aligned. // do this when all ArgRegs are used and if the outgoing slot is aligned.
@@ -437,13 +418,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
} }
// Otherwise, convert this to a FP value in int regs. // Otherwise, convert this to a FP value in int regs.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Val, FIPtr, SV);
Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
}
// FALL THROUGH // FALL THROUGH
case MVT::i64: case MVT::i64:
ObjSize = 8; ObjSize = 8;

47
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@@ -226,14 +226,8 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MF.addLiveIn(*CurArgReg++, VReg); MF.addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
// We use the stack space that is already reserved for this reg. Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); ArgValues.push_back(Arg);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
Arg, FIPtr, SV);
ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
} }
ArgOffset += 4; ArgOffset += 4;
break; break;
@@ -280,20 +274,12 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// Compose the two halves together into an i64 unit. // Compose the two halves together into an i64 unit.
SDOperand WholeValue = SDOperand WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
if (ObjectVT == MVT::i64) { // If we want a double, do a bit convert.
// If we are emitting an i64, this is what we want. if (ObjectVT == MVT::f64)
ArgValues.push_back(WholeValue); WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
} else {
assert(ObjectVT == MVT::f64); ArgValues.push_back(WholeValue);
// Otherwise, emit a store to the stack and reload into FPR.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
WholeValue, FIPtr, SV);
ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
}
} }
ArgOffset += 8; ArgOffset += 8;
break; break;
@@ -418,16 +404,11 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
ValToStore = Val; ValToStore = Val;
} else { } else {
// Convert this to a FP value in an int reg. // Convert this to a FP value in an int reg.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Val, FIPtr, SV);
Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
RegValuesToPass.push_back(Val); RegValuesToPass.push_back(Val);
} }
break; break;
case MVT::f64: { case MVT::f64:
ObjSize = 8; ObjSize = 8;
// If we can store this directly into the outgoing slot, do so. We can // If we can store this directly into the outgoing slot, do so. We can
// do this when all ArgRegs are used and if the outgoing slot is aligned. // do this when all ArgRegs are used and if the outgoing slot is aligned.
@@ -437,13 +418,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
} }
// Otherwise, convert this to a FP value in int regs. // Otherwise, convert this to a FP value in int regs.
int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand SV = DAG.getSrcValue(0);
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
Val, FIPtr, SV);
Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
}
// FALL THROUGH // FALL THROUGH
case MVT::i64: case MVT::i64:
ObjSize = 8; ObjSize = 8;