From a01b75758c740a3aba3458713b190f8ecadbe8e6 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sat, 17 Dec 2005 08:03:24 +0000
Subject: [PATCH] Implement LowerArguments, at least for the first 6 integer
 args

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24770 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Sparc/SparcISelDAGToDAG.cpp     | 65 +++++++++++++++++++++-
 lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 65 +++++++++++++++++++++-
 2 files changed, 126 insertions(+), 4 deletions(-)

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 7b7383e991b..fcc07c29f5b 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -13,8 +13,11 @@
 
 #include "SparcV8.h"
 #include "SparcV8TargetMachine.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Support/Debug.h"
 #include <iostream>
@@ -63,8 +66,66 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
 
 std::vector<SDOperand>
 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
-  assert(0 && "Unimp");
-  abort();
+  MachineFunction &MF = DAG.getMachineFunction();
+  SSARegMap *RegMap = MF.getSSARegMap();
+  std::vector<SDOperand> ArgValues;
+  
+  static const unsigned GPR[] = {
+    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
+  };
+  unsigned ArgNo = 0;
+  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
+    MVT::ValueType ObjectVT = getValueType(I->getType());
+    assert(ArgNo < 6 && "Only args in regs for now");
+    
+    switch (ObjectVT) {
+    default: assert(0 && "Unhandled argument type!");
+    // TODO: MVT::i64 & FP
+    case MVT::i1:
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32: {
+      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VReg);
+      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+      DAG.setRoot(Arg.getValue(1));
+      if (ObjectVT != MVT::i32) {
+        unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
+                                                     : ISD::AssertZext;
+        Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 
+                          DAG.getValueType(ObjectVT));
+        Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+      }
+      ArgValues.push_back(Arg);
+    }
+    }
+  }
+  
+  assert(!F.isVarArg() && "Unimp");
+  
+  // Finally, inform the code generator which regs we return values in.
+  switch (getValueType(F.getReturnType())) {
+  default: assert(0 && "Unknown type!");
+  case MVT::isVoid: break;
+  case MVT::i1:
+  case MVT::i8:
+  case MVT::i16:
+  case MVT::i32:
+    MF.addLiveOut(V8::I0);
+    break;
+  case MVT::i64:
+    MF.addLiveOut(V8::I0);
+    MF.addLiveOut(V8::I1);
+    break;
+  case MVT::f32:
+    MF.addLiveOut(V8::F0);
+    break;
+  case MVT::f64:
+    MF.addLiveOut(V8::D0);
+    break;
+  }
+  
+  return ArgValues;
 }
 
 std::pair<SDOperand, SDOperand>
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 7b7383e991b..fcc07c29f5b 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -13,8 +13,11 @@
 
 #include "SparcV8.h"
 #include "SparcV8TargetMachine.h"
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Support/Debug.h"
 #include <iostream>
@@ -63,8 +66,66 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
 
 std::vector<SDOperand>
 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
-  assert(0 && "Unimp");
-  abort();
+  MachineFunction &MF = DAG.getMachineFunction();
+  SSARegMap *RegMap = MF.getSSARegMap();
+  std::vector<SDOperand> ArgValues;
+  
+  static const unsigned GPR[] = {
+    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
+  };
+  unsigned ArgNo = 0;
+  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
+    MVT::ValueType ObjectVT = getValueType(I->getType());
+    assert(ArgNo < 6 && "Only args in regs for now");
+    
+    switch (ObjectVT) {
+    default: assert(0 && "Unhandled argument type!");
+    // TODO: MVT::i64 & FP
+    case MVT::i1:
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32: {
+      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+      MF.addLiveIn(GPR[ArgNo++], VReg);
+      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+      DAG.setRoot(Arg.getValue(1));
+      if (ObjectVT != MVT::i32) {
+        unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 
+                                                     : ISD::AssertZext;
+        Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 
+                          DAG.getValueType(ObjectVT));
+        Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+      }
+      ArgValues.push_back(Arg);
+    }
+    }
+  }
+  
+  assert(!F.isVarArg() && "Unimp");
+  
+  // Finally, inform the code generator which regs we return values in.
+  switch (getValueType(F.getReturnType())) {
+  default: assert(0 && "Unknown type!");
+  case MVT::isVoid: break;
+  case MVT::i1:
+  case MVT::i8:
+  case MVT::i16:
+  case MVT::i32:
+    MF.addLiveOut(V8::I0);
+    break;
+  case MVT::i64:
+    MF.addLiveOut(V8::I0);
+    MF.addLiveOut(V8::I1);
+    break;
+  case MVT::f32:
+    MF.addLiveOut(V8::F0);
+    break;
+  case MVT::f64:
+    MF.addLiveOut(V8::D0);
+    break;
+  }
+  
+  return ArgValues;
 }
 
 std::pair<SDOperand, SDOperand>