6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-21 02:24:22 +00:00
Code Issues Projects Releases Wiki Activity

PowerPC: Use CCBITRC operand for ISEL patterns.

Browse Source 
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand.  This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.

No change in generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
2013-03-26 10:54:54 +00:00
parent 3b25529336
commit a01c7dbaab
5 changed files with 19 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -6170,24 +6170,24 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
unsigned SelectPred = MI->getOperand(4).getImm();
DebugLoc dl = MI->getDebugLoc();
// The SelectPred is ((BI << 5) | BO) for a BCC
unsigned BO = SelectPred & 0xF;
assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel");
unsigned TrueOpNo, FalseOpNo;
if (BO == 12) {
TrueOpNo = 2;
FalseOpNo = 3;
} else {
TrueOpNo = 3;
FalseOpNo = 2;
SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred);
unsigned SubIdx;
bool SwapOps;
switch (SelectPred) {
default: llvm_unreachable("invalid predicate for isel");
case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
}
BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
.addReg(MI->getOperand(TrueOpNo).getReg())
.addReg(MI->getOperand(FalseOpNo).getReg())
.addImm(SelectPred).addReg(MI->getOperand(1).getReg());
.addReg(MI->getOperand(SwapOps? 3 : 2).getReg())
.addReg(MI->getOperand(SwapOps? 2 : 3).getReg())
.addReg(MI->getOperand(1).getReg(), 0, SubIdx);
} else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
MI->getOpcode() == PPC::SELECT_CC_I8 ||
MI->getOpcode() == PPC::SELECT_CC_F4 ||