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PowerPC: Use CCBITRC operand for ISEL patterns.

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This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand.  This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.

No change in generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
2013-03-26 10:54:54 +00:00
parent 3b25529336
commit a01c7dbaab
5 changed files with 19 additions and 46 deletions
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25
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
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@ -87,31 +87,6 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, raw_ostream &O,
const char *Modifier) { const char *Modifier) {
unsigned Code = MI->getOperand(OpNo).getImm(); unsigned Code = MI->getOperand(OpNo).getImm();
if (!Modifier) {
unsigned CCReg = MI->getOperand(OpNo+1).getReg();
unsigned RegNo;
switch (CCReg) {
default: llvm_unreachable("Unknown CR register");
case PPC::CR0: RegNo = 0; break;
case PPC::CR1: RegNo = 1; break;
case PPC::CR2: RegNo = 2; break;
case PPC::CR3: RegNo = 3; break;
case PPC::CR4: RegNo = 4; break;
case PPC::CR5: RegNo = 5; break;
case PPC::CR6: RegNo = 6; break;
case PPC::CR7: RegNo = 7; break;
}
// Print the CR bit number. The Code is ((BI << 5) | BO) for a
// BCC, but we must have the positive form here (BO == 12)
unsigned BI = Code >> 5;
assert((Code & 0xF) == 12 &&
"BO in predicate bit must have the positive form");
unsigned Value = 4*RegNo + BI;
O << Value;
return;
}
if (StringRef(Modifier) == "cc") { if (StringRef(Modifier) == "cc") {
switch ((PPC::Predicate)Code) { switch ((PPC::Predicate)Code) {

30
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -6170,24 +6170,24 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
unsigned SelectPred = MI->getOperand(4).getImm(); unsigned SelectPred = MI->getOperand(4).getImm();
DebugLoc dl = MI->getDebugLoc(); DebugLoc dl = MI->getDebugLoc();
// The SelectPred is ((BI << 5) | BO) for a BCC unsigned SubIdx;
unsigned BO = SelectPred & 0xF; bool SwapOps;
assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel"); switch (SelectPred) {
default: llvm_unreachable("invalid predicate for isel");
unsigned TrueOpNo, FalseOpNo; case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
if (BO == 12) { case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
TrueOpNo = 2; case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
FalseOpNo = 3; case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
} else { case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
TrueOpNo = 3; case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
FalseOpNo = 2; case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred); case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
} }
BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
.addReg(MI->getOperand(TrueOpNo).getReg()) .addReg(MI->getOperand(SwapOps? 3 : 2).getReg())
.addReg(MI->getOperand(FalseOpNo).getReg()) .addReg(MI->getOperand(SwapOps? 2 : 3).getReg())
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()); .addReg(MI->getOperand(1).getReg(), 0, SubIdx);
} else if (MI->getOpcode() == PPC::SELECT_CC_I4 || } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
MI->getOpcode() == PPC::SELECT_CC_I8 || MI->getOpcode() == PPC::SELECT_CC_I8 ||
MI->getOpcode() == PPC::SELECT_CC_F4 || MI->getOpcode() == PPC::SELECT_CC_F4 ||

2
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -514,7 +514,7 @@ def RLWINM8 : MForm_2<21,
[]>; []>;
def ISEL8 : AForm_4<31, 15, def ISEL8 : AForm_4<31, 15,
(outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond), (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral, "isel $rT, $rA, $rB, $cond", IntGeneral,
[]>; []>;
} // End FXU Operations. } // End FXU Operations.

6
lib/Target/PowerPC/PPCInstrFormats.td
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@ -777,16 +777,14 @@ class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
bits<5> RT; bits<5> RT;
bits<5> RA; bits<5> RA;
bits<5> RB; bits<5> RB;
bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12). bits<5> COND;
bits<3> CR;
let Pattern = pattern; let Pattern = pattern;
let Inst{6-10} = RT; let Inst{6-10} = RT;
let Inst{11-15} = RA; let Inst{11-15} = RA;
let Inst{16-20} = RB; let Inst{16-20} = RB;
let Inst{21-23} = CR; let Inst{21-25} = COND;
let Inst{24-25} = BIBO{6-5};
let Inst{26-30} = xo; let Inst{26-30} = xo;
let Inst{31} = 0; let Inst{31} = 0;
} }

2
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1482,7 +1482,7 @@ let Uses = [RM] in {
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
def ISEL : AForm_4<31, 15, def ISEL : AForm_4<31, 15,
(outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, pred:$cond), (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral, "isel $rT, $rA, $rB, $cond", IntGeneral,
[]>; []>;
} }