6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-26 18:20:39 +00:00
Code Issues Projects Releases Wiki Activity

RegisterCoalescer: Fix valuesIdentical() in some subrange merge cases.

Browse Source 
I got confused and assumed SrcIdx/DstIdx of the CoalescerPair is a
subregister index in SrcReg/DstReg, but they are actually subregister
indices of the coalesced register that get you back to SrcReg/DstReg
when applied.

Fixed the bug, improved comments and simplified code accordingly.

Testcase by Tom Stellard!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225415 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
2015-01-07 23:58:38 +00:00
parent b6eccdd6b0
commit a065cf13cd
2 changed files with 126 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

171
lib/CodeGen/RegisterCoalescer.cpp
View File

@@ -158,18 +158,16 @@ namespace {
/// Add the LiveRange @p ToMerge as a subregister liverange of @p LI. /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
/// Subranges in @p LI which only partially interfere with the desired /// Subranges in @p LI which only partially interfere with the desired
/// LaneMask are split as necessary. /// LaneMask are split as necessary. @p LaneMask are the lanes that
/// @p DestLaneMask are the lanes that @p ToMerge will end up in after the /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
/// merge, @p PrevLaneMask the ones it currently occupies. /// lanemasks already adjusted to the coalesced register.
void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge, void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
unsigned DstLaneMask, unsigned PrevLaneMask, unsigned LaneMask, CoalescerPair &CP);
CoalescerPair &CP);
/// Join the liveranges of two subregisters. Joins @p RRange into /// Join the liveranges of two subregisters. Joins @p RRange into
/// @p LRange, @p RRange may be invalid afterwards. /// @p LRange, @p RRange may be invalid afterwards.
void joinSubRegRanges(LiveRange &LRange, unsigned LMask, void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
LiveRange &RRange, unsigned RMask, unsigned LaneMask, const CoalescerPair &CP);
const CoalescerPair &CP);
/// We found a non-trivially-coalescable copy. If /// We found a non-trivially-coalescable copy. If
/// the source value number is defined by a copy from the destination reg /// the source value number is defined by a copy from the destination reg
@@ -1542,18 +1540,19 @@ class JoinVals {
/// (Main) register we work on. /// (Main) register we work on.
const unsigned Reg; const unsigned Reg;
/// When coalescing a subregister range this is the LaneMask in Reg. // Reg (and therefore the values in this liverange) will end up as subregister
unsigned SubRegMask; // SubIdx in the coalesced register. Either CP.DstIdx or CP.SrcIdx.
const unsigned SubIdx;
// The LaneMask that this liverange will occupy the coalesced register. May be
// smaller than the lanemask produced by SubIdx when merging subranges.
const unsigned LaneMask;
/// This is true when joining sub register ranges, false when joining main /// This is true when joining sub register ranges, false when joining main
/// ranges. /// ranges.
const bool SubRangeJoin; const bool SubRangeJoin;
/// Whether the current LiveInterval tracks subregister liveness. /// Whether the current LiveInterval tracks subregister liveness.
const bool TrackSubRegLiveness; const bool TrackSubRegLiveness;
// Location of this register in the final joined register.
// Either CP.DstIdx or CP.SrcIdx.
const unsigned SubIdx;
// Values that will be present in the final live range. // Values that will be present in the final live range.
SmallVectorImpl<VNInfo*> &NewVNInfo; SmallVectorImpl<VNInfo*> &NewVNInfo;
@@ -1644,7 +1643,7 @@ class JoinVals {
SmallVector<Val, 8> Vals; SmallVector<Val, 8> Vals;
unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const; unsigned computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
VNInfo *stripCopies(VNInfo *VNI, unsigned LaneMask, unsigned &Reg) const; std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const; bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other); ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
void computeAssignment(unsigned ValNo, JoinVals &Other); void computeAssignment(unsigned ValNo, JoinVals &Other);
@@ -1654,16 +1653,14 @@ class JoinVals {
bool isPrunedValue(unsigned ValNo, JoinVals &Other); bool isPrunedValue(unsigned ValNo, JoinVals &Other);
public: public:
JoinVals(LiveRange &LR, unsigned Reg, unsigned subIdx, JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, unsigned LaneMask,
SmallVectorImpl<VNInfo*> &newVNInfo, SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
const CoalescerPair &cp, LiveIntervals *lis, LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
const TargetRegisterInfo *tri, unsigned SubRegMask, bool TrackSubRegLiveness)
bool SubRangeJoin, bool TrackSubRegLiveness) : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
: LR(LR), Reg(Reg), SubRegMask(SubRegMask), SubRangeJoin(SubRangeJoin), SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
TrackSubRegLiveness(TrackSubRegLiveness), SubIdx(subIdx),
NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()), NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
TRI(tri), Assignments(LR.getNumValNums(), -1), TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums())
Vals(LR.getNumValNums())
{} {}
/// Analyze defs in LR and compute a value mapping in NewVNInfo. /// Analyze defs in LR and compute a value mapping in NewVNInfo.
@@ -1715,29 +1712,33 @@ unsigned JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
} }
/// Find the ultimate value that VNI was copied from. /// Find the ultimate value that VNI was copied from.
VNInfo *JoinVals::stripCopies(VNInfo *VNI, unsigned LaneMask, unsigned &Reg) std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
const { const VNInfo *VNI) const {
unsigned Reg = this->Reg;
while (!VNI->isPHIDef()) { while (!VNI->isPHIDef()) {
SlotIndex Def = VNI->def; SlotIndex Def = VNI->def;
MachineInstr *MI = Indexes->getInstructionFromIndex(Def); MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
assert(MI && "No defining instruction"); assert(MI && "No defining instruction");
if (!MI->isFullCopy()) if (!MI->isFullCopy())
return VNI; return std::make_pair(VNI, Reg);
unsigned SrcReg = MI->getOperand(1).getReg(); unsigned SrcReg = MI->getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
return VNI; return std::make_pair(VNI, Reg);
const LiveInterval &LI = LIS->getInterval(SrcReg); const LiveInterval &LI = LIS->getInterval(SrcReg);
VNInfo *ValueIn; const VNInfo *ValueIn;
// No subrange involved. // No subrange involved.
if (LaneMask == 0 || !LI.hasSubRanges()) { if (!SubRangeJoin || !LI.hasSubRanges()) {
LiveQueryResult LRQ = LI.Query(Def); LiveQueryResult LRQ = LI.Query(Def);
ValueIn = LRQ.valueIn(); ValueIn = LRQ.valueIn();
} else { } else {
// Query subranges. Pick the first matching one. // Query subranges. Pick the first matching one.
ValueIn = nullptr; ValueIn = nullptr;
for (const LiveInterval::SubRange &S : LI.subranges()) { for (const LiveInterval::SubRange &S : LI.subranges()) {
if ((S.LaneMask & LaneMask) == 0) // Transform lanemask to a mask in the joined live interval.
unsigned SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
if ((SMask & LaneMask) == 0)
continue; continue;
LiveQueryResult LRQ = S.Query(Def); LiveQueryResult LRQ = S.Query(Def);
ValueIn = LRQ.valueIn(); ValueIn = LRQ.valueIn();
@@ -1749,22 +1750,26 @@ VNInfo *JoinVals::stripCopies(VNInfo *VNI, unsigned LaneMask, unsigned &Reg)
VNI = ValueIn; VNI = ValueIn;
Reg = SrcReg; Reg = SrcReg;
} }
return VNI; return std::make_pair(VNI, Reg);
} }
bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1, bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
const JoinVals &Other) const { const JoinVals &Other) const {
unsigned Reg0 = Reg; const VNInfo *Orig0;
VNInfo *Stripped0 = stripCopies(Value0, SubRegMask, Reg0); unsigned Reg0;
unsigned Reg1 = Other.Reg; std::tie(Orig0, Reg0) = followCopyChain(Value0);
VNInfo *Stripped1 = stripCopies(Value1, Other.SubRegMask, Reg1); if (Orig0 == Value1)
if (Stripped0 == Stripped1)
return true; return true;
// Special case: when merging subranges one of the ranges is actually a copy, const VNInfo *Orig1;
// so we can't simply compare VNInfos but have to resort to comparing unsigned Reg1;
// position and register of the Def. std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
return Stripped0->def == Stripped1->def && Reg0 == Reg1;
// The values are equal if they are defined at the same place and use the
// same register. Note that we cannot compare VNInfos directly as some of
// them might be from a copy created in mergeSubRangeInto() while the other
// is from the original LiveInterval.
return Orig0->def == Orig1->def && Reg0 == Reg1;
} }
/// Analyze ValNo in this live range, and set all fields of Vals[ValNo]. /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
@@ -2340,14 +2345,14 @@ void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
} }
} }
void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, unsigned LMask, void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
LiveRange &RRange, unsigned RMask, unsigned LaneMask,
const CoalescerPair &CP) { const CoalescerPair &CP) {
SmallVector<VNInfo*, 16> NewVNInfo; SmallVector<VNInfo*, 16> NewVNInfo;
JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
NewVNInfo, CP, LIS, TRI, LMask, true, true); NewVNInfo, CP, LIS, TRI, true, true);
JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
NewVNInfo, CP, LIS, TRI, RMask, true, true); NewVNInfo, CP, LIS, TRI, true, true);
/// Compute NewVNInfo and resolve conflicts (see also joinVirtRegs()) /// Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
/// Conflicts should already be resolved so the mapping/resolution should /// Conflicts should already be resolved so the mapping/resolution should
@@ -2385,14 +2390,12 @@ void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, unsigned LMask,
void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI, void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
const LiveRange &ToMerge, const LiveRange &ToMerge,
unsigned DstLaneMask, unsigned LaneMask, CoalescerPair &CP) {
unsigned PrevLaneMask,
CoalescerPair &CP) {
BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
for (LiveInterval::SubRange &R : LI.subranges()) { for (LiveInterval::SubRange &R : LI.subranges()) {
unsigned RMask = R.LaneMask; unsigned RMask = R.LaneMask;
// LaneMask of subregisters common to subrange R and ToMerge. // LaneMask of subregisters common to subrange R and ToMerge.
unsigned Common = RMask & DstLaneMask; unsigned Common = RMask & LaneMask;
// There is nothing to do without common subregs. // There is nothing to do without common subregs.
if (Common == 0) if (Common == 0)
continue; continue;
@@ -2400,7 +2403,7 @@ void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
DEBUG(dbgs() << format("\t\tCopy+Merge %04X into %04X\n", RMask, Common)); DEBUG(dbgs() << format("\t\tCopy+Merge %04X into %04X\n", RMask, Common));
// LaneMask of subregisters contained in the R range but not in ToMerge, // LaneMask of subregisters contained in the R range but not in ToMerge,
// they have to split into their own subrange. // they have to split into their own subrange.
unsigned LRest = RMask & ~DstLaneMask; unsigned LRest = RMask & ~LaneMask;
LiveInterval::SubRange *CommonRange; LiveInterval::SubRange *CommonRange;
if (LRest != 0) { if (LRest != 0) {
R.LaneMask = LRest; R.LaneMask = LRest;
@@ -2413,14 +2416,13 @@ void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
CommonRange = &R; CommonRange = &R;
} }
LiveRange RangeCopy(ToMerge, Allocator); LiveRange RangeCopy(ToMerge, Allocator);
joinSubRegRanges(*CommonRange, CommonRange->LaneMask, RangeCopy, joinSubRegRanges(*CommonRange, RangeCopy, Common, CP);
PrevLaneMask, CP); LaneMask &= ~RMask;
DstLaneMask &= ~RMask;
} }
if (DstLaneMask != 0) { if (LaneMask != 0) {
DEBUG(dbgs() << format("\t\tNew Lane %04X\n", DstLaneMask)); DEBUG(dbgs() << format("\t\tNew Lane %04X\n", LaneMask));
LI.createSubRangeFrom(Allocator, DstLaneMask, ToMerge); LI.createSubRangeFrom(Allocator, LaneMask, ToMerge);
} }
} }
@@ -2429,10 +2431,10 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg()); LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
LiveInterval &LHS = LIS->getInterval(CP.getDstReg()); LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
bool TrackSubRegLiveness = MRI->tracksSubRegLiveness(); bool TrackSubRegLiveness = MRI->tracksSubRegLiveness();
JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), NewVNInfo, CP, LIS, TRI, JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), 0, NewVNInfo, CP, LIS,
0, false, TrackSubRegLiveness); TRI, false, TrackSubRegLiveness);
JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), NewVNInfo, CP, LIS, TRI, JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), 0, NewVNInfo, CP, LIS,
0, false, TrackSubRegLiveness); TRI, false, TrackSubRegLiveness);
DEBUG(dbgs() << "\t\tRHS = " << RHS DEBUG(dbgs() << "\t\tRHS = " << RHS
<< "\n\t\tLHS = " << LHS << "\n\t\tLHS = " << LHS
@@ -2450,48 +2452,37 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
// All clear, the live ranges can be merged. // All clear, the live ranges can be merged.
if (RHS.hasSubRanges() || LHS.hasSubRanges()) { if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
// Transform lanemasks from the LHS to masks in the coalesced register and
// create initial subranges if necessary.
unsigned DstIdx = CP.getDstIdx(); unsigned DstIdx = CP.getDstIdx();
if (!LHS.hasSubRanges()) { if (!LHS.hasSubRanges()) {
unsigned Mask = CP.getNewRC()->getLaneMask(); unsigned Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
unsigned DstMask = TRI->composeSubRegIndexLaneMask(DstIdx, Mask); : TRI->getSubRegIndexLaneMask(DstIdx);
// LHS must support subregs or we wouldn't be in this codepath. // LHS must support subregs or we wouldn't be in this codepath.
assert(DstMask != 0); assert(Mask != 0);
LHS.createSubRangeFrom(Allocator, DstMask, LHS); LHS.createSubRangeFrom(Allocator, Mask, LHS);
DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg())
<< ' ' << LHS << '\n');
} else if (DstIdx != 0) { } else if (DstIdx != 0) {
// Transform LHS lanemasks to new register class if necessary. // Transform LHS lanemasks to new register class if necessary.
for (LiveInterval::SubRange &R : LHS.subranges()) { for (LiveInterval::SubRange &R : LHS.subranges()) {
unsigned DstMask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask); unsigned Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
R.LaneMask = DstMask; R.LaneMask = Mask;
} }
DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg())
<< ' ' << LHS << '\n');
} }
DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg())
<< ' ' << LHS << '\n');
// Determine lanemasks of RHS in the coalesced register and merge subranges.
unsigned SrcIdx = CP.getSrcIdx(); unsigned SrcIdx = CP.getSrcIdx();
if (!RHS.hasSubRanges()) { if (!RHS.hasSubRanges()) {
unsigned Mask = SrcIdx != 0 unsigned Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
? TRI->getSubRegIndexLaneMask(SrcIdx) : TRI->getSubRegIndexLaneMask(SrcIdx);
: MRI->getMaxLaneMaskForVReg(LHS.reg); mergeSubRangeInto(LHS, RHS, Mask, CP);
DEBUG(dbgs() << "\t\tRHS Mask: "
<< format("%04X", Mask) << "\n");
mergeSubRangeInto(LHS, RHS, Mask, 0, CP);
} else { } else {
// Pair up subranges and merge. // Pair up subranges and merge.
for (LiveInterval::SubRange &R : RHS.subranges()) { for (LiveInterval::SubRange &R : RHS.subranges()) {
unsigned RMask = R.LaneMask; unsigned Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
if (SrcIdx != 0) { mergeSubRangeInto(LHS, R, Mask, CP);
// Transform LaneMask of RHS subranges to the ones on LHS.
RMask = TRI->composeSubRegIndexLaneMask(SrcIdx, RMask);
DEBUG(dbgs() << "\t\tTransform RHS Mask "
<< format("%04X", R.LaneMask) << " to subreg "
<< TRI->getSubRegIndexName(SrcIdx)
<< " => " << format("%04X", RMask) << "\n");
}
mergeSubRangeInto(LHS, R, RMask, R.LaneMask, CP);
} }
} }

45
test/CodeGen/R600/subreg-coalescer-crash.ll Normal file
View File

@@ -0,0 +1,45 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs -o - %s
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"
; SI: s_endpgm
; Function Attrs: nounwind
define void @row_filter_C1_D0() #0 {
entry:
br i1 undef, label %for.inc.1, label %do.body.preheader
do.body.preheader: ; preds = %entry
%0 = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
br i1 undef, label %do.body56.1, label %do.body90
do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
%1 = phi <4 x i32> [ %6, %do.body56.2 ], [ %5, %do.body56.1 ], [ %0, %do.body.preheader ]
%2 = insertelement <4 x i32> %1, i32 undef, i32 2
%3 = insertelement <4 x i32> %2, i32 undef, i32 3
br i1 undef, label %do.body124.1, label %do.body.1562.preheader
do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
%storemerge = phi <4 x i32> [ %3, %do.body90 ], [ %7, %do.body124.1 ]
%4 = insertelement <4 x i32> undef, i32 undef, i32 1
br label %for.inc.1
do.body56.1: ; preds = %do.body.preheader
%5 = insertelement <4 x i32> %0, i32 undef, i32 1
%or.cond472.1 = or i1 undef, undef
br i1 %or.cond472.1, label %do.body56.2, label %do.body90
do.body56.2: ; preds = %do.body56.1
%6 = insertelement <4 x i32> %5, i32 undef, i32 1
br label %do.body90
do.body124.1: ; preds = %do.body90
%7 = insertelement <4 x i32> %3, i32 undef, i32 3
br label %do.body.1562.preheader
for.inc.1: ; preds = %do.body.1562.preheader, %entry
%storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
%add.i495 = add <4 x i32> %storemerge591, undef
unreachable
}