mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-23 00:20:25 +00:00
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -527,10 +527,10 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
|
||||
MachineInstr *DefMI = Def->getInstr();
|
||||
int DefIdx = DefMI->findRegisterDefOperandIdx(Reg);
|
||||
if (DefIdx != -1) {
|
||||
unsigned DefClass = DefMI->getDesc().getSchedClass();
|
||||
MachineInstr *UseMI = Use->getInstr();
|
||||
unsigned UseClass = UseMI->getDesc().getSchedClass();
|
||||
const TargetInstrDesc &DefTID = DefMI->getDesc();
|
||||
unsigned DefClass = DefTID.getSchedClass();
|
||||
|
||||
MachineInstr *UseMI = Use->getInstr();
|
||||
// For all uses of the register, calculate the maxmimum latency
|
||||
int Latency = -1;
|
||||
for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
|
||||
@@ -541,8 +541,7 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use,
|
||||
if (MOReg != Reg)
|
||||
continue;
|
||||
|
||||
int UseCycle = InstrItins->getOperandLatency(DefClass, DefIdx,
|
||||
UseClass, i);
|
||||
int UseCycle = TII->getOperandLatency(InstrItins, DefMI, DefIdx, UseMI, i);
|
||||
Latency = std::max(Latency, UseCycle);
|
||||
|
||||
// If we found a latency, then replace the existing dependence latency.
|
||||
|
||||
Reference in New Issue
Block a user