6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 06:32:24 +00:00
Code Issues Projects Releases Wiki Activity

[ppc] Distinguish the 'es', 'o', 'm', 'Q', 'Z', and 'Zy' inline assembly memory constraints.

Browse Source 
Summary:
But still handle them the same way since I don't know how they differ on
this target.

Of these, 'es', and 'Q' do not have backend tests but are accepted by
clang.

No functional change intended. Depends on D8173.

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232466 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-03-17 11:09:13 +00:00
parent 0401f798d1
commit a0a7510711
3 changed files with 41 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/IR/InlineAsm.h
View File

@ -239,10 +239,14 @@ public:
// there's plenty of space in the encoding to support the union of all // there's plenty of space in the encoding to support the union of all
// constraint codes for all targets. // constraint codes for all targets.
Constraint_Unknown = 0, Constraint_Unknown = 0,
Constraint_es,
Constraint_m, Constraint_m,
Constraint_o, // Unused at the moment since Constraint_m is always used. Constraint_o,
Constraint_v, // Unused at the moment since Constraint_m is always used. Constraint_v, // Unused at the moment since Constraint_m is always used.
Constraints_Max = Constraint_v, Constraint_Q,
Constraint_Z,
Constraint_Zy,
Constraints_Max = Constraint_Zy,
Constraints_ShiftAmount = 16, Constraints_ShiftAmount = 16,
Flag_MatchingOperand = 0x80000000 Flag_MatchingOperand = 0x80000000

35
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -188,18 +188,31 @@ namespace {
bool SelectInlineAsmMemoryOperand(const SDValue &Op, bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override { std::vector<SDValue> &OutOps) override {
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).
const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
SDValue NewOp =
SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
SDLoc(Op), Op.getValueType(),
Op, RC), 0);
OutOps.push_back(NewOp); switch(ConstraintID) {
return false; default:
errs() << "ConstraintID: " << ConstraintID << "\n";
llvm_unreachable("Unexpected asm memory constraint");
case InlineAsm::Constraint_es:
case InlineAsm::Constraint_m:
case InlineAsm::Constraint_o:
case InlineAsm::Constraint_Q:
case InlineAsm::Constraint_Z:
case InlineAsm::Constraint_Zy:
// We need to make sure that this one operand does not end up in r0
// (because we might end up lowering this as 0(%op)).
const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
SDValue NewOp =
SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
SDLoc(Op), Op.getValueType(),
Op, RC), 0);
OutOps.push_back(NewOp);
return false;
}
return true;
} }
void InsertVRSaveCode(MachineFunction &MF); void InsertVRSaveCode(MachineFunction &MF);

13
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -521,8 +521,17 @@ namespace llvm {
unsigned getInlineAsmMemConstraint( unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override { const std::string &ConstraintCode) const override {
// FIXME: Map different constraints differently. if (ConstraintCode == "es")
return InlineAsm::Constraint_m; return InlineAsm::Constraint_es;
else if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
else if (ConstraintCode == "Q")
return InlineAsm::Constraint_Q;
else if (ConstraintCode == "Z")
return InlineAsm::Constraint_Z;
else if (ConstraintCode == "Zy")
return InlineAsm::Constraint_Zy;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
} }
/// isLegalAddressingMode - Return true if the addressing mode represented /// isLegalAddressingMode - Return true if the addressing mode represented