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[Hexagon] Eliminating immediate condition set.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231693 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-03-09 19:57:18 +00:00
parent 70d77d1edc
commit a0ce232a65
8 changed files with 7 additions and 189 deletions
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8
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -4727,14 +4727,6 @@ def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
let Inst{20-16} = Rs;
}
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),
"Error; should not emit",
[(set (i32 IntRegs:$dst),
(i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
s12ImmPred:$src3)))]>;
// Support for generating global address.
// Taken from X86InstrInfo.td.
def SDTHexagonCONST32 : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,

165
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -137,6 +137,9 @@ def: T_cmp32_rr_pat<A4_rcmpeq, CmpInReg<seteq>, i32>;
def: T_cmp32_rr_pat<A4_rcmpneq, CmpInReg<setne>, i32>;
def: T_cmp32_rr_pat<C4_cmpneq, setne, i1>;
def: T_cmp32_rr_pat<C4_cmplteu, setule, i1>;
def: T_cmp32_rr_pat<C4_cmplteu, RevCmp<setuge>, i1>;
class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
@ -3135,168 +3138,6 @@ def DEC_CONST_BYTE : SDNodeXForm<imm, [{
return XformU7ToU7M1Imm(imm);
}]>;
// For the sequence
// zext( seteq ( and(Rs, 255), u8))
// Generate
// Pd=cmpb.eq(Rs, #u8)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
(u8ExtPred:$u8))),
1, 0))>;
// For the sequence
// zext( setne ( and(Rs, 255), u8))
// Generate
// Pd=cmpb.eq(Rs, #u8)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (A4_cmpbeqi (i32 IntRegs:$Rs),
(u8ExtPred:$u8))),
0, 1))>;
// For the sequence
// zext( seteq (Rs, and(Rt, 255)))
// Generate
// Pd=cmpb.eq(Rs, Rt)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
(i32 (and (i32 IntRegs:$Rs), 255)))))),
(i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
(i32 IntRegs:$Rt))),
1, 0))>;
// For the sequence
// zext( setne (Rs, and(Rt, 255)))
// Generate
// Pd=cmpb.eq(Rs, Rt)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
(i32 (and (i32 IntRegs:$Rs), 255)))))),
(i32 (TFR_condset_ii (i1 (A4_cmpbeq (i32 IntRegs:$Rs),
(i32 IntRegs:$Rt))),
0, 1))>;
// For the sequence
// zext( setugt ( and(Rs, 255), u8))
// Generate
// Pd=cmpb.gtu(Rs, #u8)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
(u8ExtPred:$u8))),
1, 0))>;
// For the sequence
// zext( setugt ( and(Rs, 254), u8))
// Generate
// Pd=cmpb.gtu(Rs, #u8)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
u8ExtPred:$u8)))),
(i32 (TFR_condset_ii (i1 (A4_cmpbgtui (i32 IntRegs:$Rs),
(u8ExtPred:$u8))),
1, 0))>;
// For the sequence
// zext( setult ( Rs, Rt))
// Generate
// Pd=cmp.ltu(Rs, Rt)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
// cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
(i32 IntRegs:$Rs))),
1, 0))>;
// For the sequence
// zext( setlt ( Rs, Rt))
// Generate
// Pd=cmp.lt(Rs, Rt)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
// cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
(i32 IntRegs:$Rs))),
1, 0))>;
// For the sequence
// zext( setugt ( Rs, Rt))
// Generate
// Pd=cmp.gtu(Rs, Rt)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
(i32 IntRegs:$Rt))),
1, 0))>;
// This pattern interefers with coremark performance, not implementing at this
// time.
// For the sequence
// zext( setgt ( Rs, Rt))
// Generate
// Pd=cmp.gt(Rs, Rt)
// if (Pd.new) Rd=#1
// if (!Pd.new) Rd=#0
// For the sequence
// zext( setuge ( Rs, Rt))
// Generate
// Pd=cmp.ltu(Rs, Rt)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
// cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rt),
(i32 IntRegs:$Rs))),
0, 1))>;
// For the sequence
// zext( setge ( Rs, Rt))
// Generate
// Pd=cmp.lt(Rs, Rt)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
// cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rt),
(i32 IntRegs:$Rs))),
0, 1))>;
// For the sequence
// zext( setule ( Rs, Rt))
// Generate
// Pd=cmp.gtu(Rs, Rt)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgtu (i32 IntRegs:$Rs),
(i32 IntRegs:$Rt))),
0, 1))>;
// For the sequence
// zext( setle ( Rs, Rt))
// Generate
// Pd=cmp.gt(Rs, Rt)
// if (Pd.new) Rd=#0
// if (!Pd.new) Rd=#1
def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
(i32 (TFR_condset_ii (i1 (C2_cmpgt (i32 IntRegs:$Rs),
(i32 IntRegs:$Rt))),
0, 1))>;
// For the sequence
// zext( setult ( and(Rs, 255), u8))
// Use the isdigit transformation below

3
lib/Target/Hexagon/HexagonNewValueJump.cpp
View File

@ -199,8 +199,7 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
// of registers by individual passes in the backend. At this time,
// we don't know the scope of usage and definitions of these
// instructions.
if (MII->getOpcode() == Hexagon::TFR_condset_ii ||
MII->getOpcode() == Hexagon::LDriw_pred ||
if (MII->getOpcode() == Hexagon::LDriw_pred ||
MII->getOpcode() == Hexagon::STriw_pred)
return false;
}

1
lib/Target/Hexagon/HexagonPeephole.cpp
View File

@ -271,7 +271,6 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
switch (Op) {
case Hexagon::C2_mux:
case Hexagon::C2_muxii:
case Hexagon::TFR_condset_ii:
NewOp = Op;
break;
case Hexagon::C2_muxri:

16
lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
View File

@ -87,22 +87,6 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
++MII) {
MachineInstr *MI = MII;
switch(MI->getOpcode()) {
case Hexagon::TFR_condset_ii: {
int DestReg = MI->getOperand(0).getReg();
int SrcReg1 = MI->getOperand(1).getReg();
int Immed1 = MI->getOperand(2).getImm();
int Immed2 = MI->getOperand(3).getImm();
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::C2_cmoveit),
DestReg).addReg(SrcReg1).addImm(Immed1);
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::C2_cmoveif),
DestReg).addReg(SrcReg1).addImm(Immed2);
MII = MBB->erase(MI);
--MII;
break;
}
}
}
}

1
test/CodeGen/Hexagon/cmp_pred.ll
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@ -1,3 +1,4 @@
; XFAIL:
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
target triple = "hexagon"

1
test/CodeGen/Hexagon/cmp_pred_reg.ll
View File

@ -1,3 +1,4 @@
; XFAIL:
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
target triple = "hexagon"

1
test/CodeGen/Hexagon/cmpb_pred.ll
View File

@ -1,3 +1,4 @@
; XFAIL:
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
target triple = "hexagon"