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1. Fix a leftover bug in generating memory instructions.
2. Fix type used for TmpInstruction holding the return address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2075 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -918,19 +918,20 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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// The major work here is to extract these for all 3 instruction types
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// and then call the common function SetMemOperands_Internal().
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//
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vector<Value*> idxVec;
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Value* ptrVal = memInst->getPointerOperand();
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// Test if a GetElemPtr instruction is being folded into this mem instrn.
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// If so, it will be in the left child for Load and GetElemPtr,
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// and in the right child for Store instructions.
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//
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// Start with the index vector of this instruction, if any.
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vector<Value*> idxVec;
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idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
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// If there is a GetElemPtr instruction to fold in to this instr,
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// it must be in the left child for Load and GetElemPtr, and in the
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// right child for Store instructions.
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InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
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? vmInstrNode->rightChild()
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: vmInstrNode->leftChild());
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// Fold chains of GetElemPtr instructions for structure references.
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//
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if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
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&& (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
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ptrChild->getOpLabel() == GetElemPtrIdx))
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@ -940,10 +941,6 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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ptrVal = newPtr;
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}
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// Append the index vector of this instruction (may be none) to the indexes
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// folded in previous getElementPtr's (may be none)
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idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
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SetMemOperands_Internal(mvec, mvecI, vmInstrNode, ptrVal, idxVec, target);
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}
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@ -1044,16 +1041,30 @@ SetMemOperands_Internal(vector<MachineInstr*>& mvec,
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smallConstOffset = 0;
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}
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// Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR
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// It is the left child in the instruction tree in all cases.
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Value* leftVal = vmInstrNode->leftChild()->getValue();
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(*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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leftVal);
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// For STORE:
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// Operand 0 is value, operand 1 is ptr, operand 2 is offset
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// For LOAD or GET_ELEMENT_PTR,
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// Operand 0 is ptr, operand 1 is offset, operand 2 is result.
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//
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unsigned offsetOpNum, ptrOpNum;
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if (memInst->getOpcode() == Instruction::Store)
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{
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(*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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vmInstrNode->leftChild()->getValue());
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ptrOpNum = 1;
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offsetOpNum = 2;
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}
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else
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{
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ptrOpNum = 0;
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offsetOpNum = 1;
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(*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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memInst);
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}
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(*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
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ptrVal);
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// Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR
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// Operand 2 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
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//
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unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1;
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if (offsetOpType == MachineOperand::MO_VirtualRegister)
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{
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assert(valueForRegOffset != NULL);
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@ -1063,13 +1074,6 @@ SetMemOperands_Internal(vector<MachineInstr*>& mvec,
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else
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(*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
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smallConstOffset);
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if (memInst->getOpcode() == Instruction::Store)
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(*mvecI)->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
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ptrVal);
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else
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(*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
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vmInstrNode->getValue());
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}
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@ -2089,17 +2093,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
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Value *callee = callInstr->getCalledValue();
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Instruction* retAddrReg = new TmpInstruction(callInstr);
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// Note temporary values in the machineInstrVec for the VM instr.
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//
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// WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
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// The result value must go in slot N. This is assumed
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// in register allocation.
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//
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// Create hidden virtual register for return address, with type void*.
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Instruction* retAddrReg =
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new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
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MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
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// Generate the machine instruction and its operands.
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// Use CALL for direct function calls; this optimistically assumes
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// the PC-relative address fits in the CALL address field (22 bits).
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@ -2123,7 +2121,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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}
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mvec.push_back(M);
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// WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
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// The result value must go in slot N. This is assumed
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// in register allocation.
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//
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// Add the call operands and return value as implicit refs
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for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
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if (callInstr->getOperand(i) != callee)
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