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setOperand should not zap the operand list or add implicit operands to an
instruction. Doing so breaks the FP stackifier, the alpha branch selector the sparc fpmover. This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31876 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -490,7 +490,7 @@ public:
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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///
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void setOpcode(unsigned Op);
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void setOpcode(unsigned Op) { Opcode = Op; }
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/// RemoveOperand - Erase an operand from an instruction, leaving it with one
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/// fewer operand than it started with.
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@ -180,45 +180,6 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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}
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}
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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///
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void MachineInstr::setOpcode(unsigned Op) {
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Operands.erase(Operands.begin(), Operands.begin()+NumImplicitOps);
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NumImplicitOps = 0;
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Opcode = Op;
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if (!getParent())
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return;
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const TargetInstrDescriptor &TID = getParent()->getParent()->
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getTarget().getInstrInfo()->get(Op);
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if (TID.ImplicitDefs)
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for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = true;
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Op.IsImp = true;
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Op.IsKill = false;
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Op.IsDead = false;
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Op.contents.RegNo = *ImpDefs;
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Op.offset = 0;
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Operands.insert(Operands.begin()+NumImplicitOps, Op);
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NumImplicitOps++;
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}
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if (TID.ImplicitUses)
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for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses) {
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MachineOperand Op;
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Op.opType = MachineOperand::MO_Register;
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Op.IsDef = false;
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Op.IsImp = true;
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Op.IsKill = false;
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Op.IsDead = false;
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Op.contents.RegNo = *ImpUses;
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Op.offset = 0;
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Operands.insert(Operands.begin()+NumImplicitOps, Op);
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NumImplicitOps++;
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}
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}
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void MachineInstr::dump() const {
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std::cerr << " " << *this;
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}
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