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LoopVectorizer: Enable unrolling of conditional stores and the load/store

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unrolling heuristic per default

Benchmarking on x86_64 (thanks Chandler!) and ARM has shown those options speed
up some benchmarks while not causing any interesting regressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200621 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2014-02-02 03:12:34 +00:00
parent 1bdadf38ef
commit a16c1b55e2
2 changed files with 6 additions and 3 deletions
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6
lib/Transforms/Vectorize/LoopVectorize.cpp
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@ -180,16 +180,16 @@ static cl::opt<bool> LoopVectorizeWithBlockFrequency(
// Runtime unroll loops for load/store throughput. // Runtime unroll loops for load/store throughput.
static cl::opt<bool> EnableLoadStoreRuntimeUnroll( static cl::opt<bool> EnableLoadStoreRuntimeUnroll(
"enable-loadstore-runtime-unroll", cl::init(false), cl::Hidden, "enable-loadstore-runtime-unroll", cl::init(true), cl::Hidden,
cl::desc("Enable runtime unrolling until load/store ports are saturated")); cl::desc("Enable runtime unrolling until load/store ports are saturated"));
/// The number of stores in a loop that are allowed to need predication. /// The number of stores in a loop that are allowed to need predication.
static cl::opt<unsigned> NumberOfStoresToPredicate( static cl::opt<unsigned> NumberOfStoresToPredicate(
"vectorize-num-stores-pred", cl::init(0), cl::Hidden, "vectorize-num-stores-pred", cl::init(1), cl::Hidden,
cl::desc("Max number of stores to be predicated behind an if.")); cl::desc("Max number of stores to be predicated behind an if."));
static cl::opt<bool> EnableIndVarRegisterHeur( static cl::opt<bool> EnableIndVarRegisterHeur(
"enable-ind-var-reg-heur", cl::init(false), cl::Hidden, "enable-ind-var-reg-heur", cl::init(true), cl::Hidden,
cl::desc("Count the induction variable only once when unrolling")); cl::desc("Count the induction variable only once when unrolling"));
static cl::opt<bool> EnableCondStoresVectorization( static cl::opt<bool> EnableCondStoresVectorization(

3
test/Transforms/LoopVectorize/ARM/arm-unroll.ll
View File

@ -47,6 +47,7 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) {
%sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ] %sum.03 = phi i32 [ %7, %.lr.ph ], [ 0, %0 ]
%sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ] %sum.04 = phi i32 [ %8, %.lr.ph ], [ 0, %0 ]
%sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ] %sum.05 = phi i32 [ %9, %.lr.ph ], [ 0, %0 ]
%sum.06 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
%2 = getelementptr inbounds i32* %A, i32 %i.02 %2 = getelementptr inbounds i32* %A, i32 %i.02
%3 = load i32* %2, align 4 %3 = load i32* %2, align 4
%4 = add nsw i32 %3, %sum.01 %4 = add nsw i32 %3, %sum.01
@ -55,6 +56,7 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) {
%7 = add nsw i32 %3, %sum.03 %7 = add nsw i32 %3, %sum.03
%8 = add nsw i32 %3, %sum.04 %8 = add nsw i32 %3, %sum.04
%9 = add nsw i32 %3, %sum.05 %9 = add nsw i32 %3, %sum.05
%10 = add nsw i32 %3, %sum.05
%exitcond = icmp eq i32 %5, %n %exitcond = icmp eq i32 %5, %n
br i1 %exitcond, label %._crit_edge, label %.lr.ph br i1 %exitcond, label %._crit_edge, label %.lr.ph
@ -64,5 +66,6 @@ define i32 @register_limit(i32* nocapture %A, i32 %n) {
%sum.2.lcssa = phi i32 [ 0, %0 ], [ %7, %.lr.ph ] %sum.2.lcssa = phi i32 [ 0, %0 ], [ %7, %.lr.ph ]
%sum.4.lcssa = phi i32 [ 0, %0 ], [ %8, %.lr.ph ] %sum.4.lcssa = phi i32 [ 0, %0 ], [ %8, %.lr.ph ]
%sum.5.lcssa = phi i32 [ 0, %0 ], [ %9, %.lr.ph ] %sum.5.lcssa = phi i32 [ 0, %0 ], [ %9, %.lr.ph ]
%sum.6.lcssa = phi i32 [ 0, %0 ], [ %10, %.lr.ph ]
ret i32 %sum.0.lcssa ret i32 %sum.0.lcssa
} }