mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-02 07:32:52 +00:00
Lower vector compares to VCMP nodes, just like we lower vector comparison
predicates to VCMPo nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
8f5d316ff2
commit
a17b1557ad
@ -235,6 +235,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::CALL: return "PPCISD::CALL";
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case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
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case PPCISD::MFCR: return "PPCISD::MFCR";
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case PPCISD::VCMP: return "PPCISD::VCMP";
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case PPCISD::VCMPo: return "PPCISD::VCMPo";
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}
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}
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@ -752,31 +753,53 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
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unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
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unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue();
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// If this is a lowered altivec predicate compare, CompareOpc is set to the
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// opcode number of the comparison.
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int CompareOpc = -1;
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bool isDot = false;
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switch (IntNo) {
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default: return SDOperand(); // Don't custom lower most intrinsics.
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case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; break;
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case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; break;
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case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; break;
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case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; break;
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case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; break;
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case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; break;
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case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; break;
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case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; break;
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case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; break;
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case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; break;
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case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; break;
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case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; break;
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case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; break;
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// Comparison predicates.
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case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
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case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
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// Normal Comparisons.
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case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
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case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
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}
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assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
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// If this is a non-dot comparison, make the VCMP node.
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if (!isDot)
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return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
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Op.getOperand(1), Op.getOperand(2),
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DAG.getConstant(CompareOpc, MVT::i32));
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// Create the PPCISD altivec 'dot' comparison node.
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std::vector<SDOperand> Ops;
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std::vector<MVT::ValueType> VTs;
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@ -85,6 +85,12 @@ namespace llvm {
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/// This copies the bits corresponding to the specified CRREG into the
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/// resultant GPR. Bits corresponding to other CR regs are undefined.
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MFCR,
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/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
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/// instructions. For lack of better number, we use the opcode number
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/// encoding for the OPC field to identify the compare. For example, 838
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/// is VCMPGTSH.
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VCMP,
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/// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
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/// altivec VCMP*o instructions. For lack of better number, we use the
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@ -453,32 +453,32 @@ def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
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// f32 element comparisons.
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def VCMPBFP : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpbfp $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4f32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 966)))]>;
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def VCMPBFPo : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpbfp. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4f32
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 966)))]>, isVDOT;
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def VCMPEQFP : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpeqfp $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4f32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 198)))]>;
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def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4f32
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 198)))]>, isVDOT;
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def VCMPGEFP : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgefp $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4f32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 454)))]>;
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def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgefp. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4f32
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 454)))]>, isVDOT;
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def VCMPGTFP : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtfp $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4f32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 710)))]>;
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def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4f32
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@ -487,24 +487,24 @@ def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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// i8 element comparisons.
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def VCMPEQUB : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequb $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v16i8
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(PPCvcmp VRRC:$vA, VRRC:$vB, 6)))]>;
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def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequb. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v16i8
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 6)))]>, isVDOT;
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def VCMPGTSB : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsb $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v16i8
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(PPCvcmp VRRC:$vA, VRRC:$vB, 774)))]>;
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def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v16i8
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 774)))]>, isVDOT;
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def VCMPGTUB : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtub $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v16i8
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(PPCvcmp VRRC:$vA, VRRC:$vB, 518)))]>;
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def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtub. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v16i8
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@ -513,24 +513,24 @@ def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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// i16 element comparisons.
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def VCMPEQUH : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequh $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v8i16
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(PPCvcmp VRRC:$vA, VRRC:$vB, 70)))]>;
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def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequh. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v8i16
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 70)))]>, isVDOT;
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def VCMPGTSH : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsh $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v8i16
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(PPCvcmp VRRC:$vA, VRRC:$vB, 838)))]>;
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def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v8i16
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 838)))]>, isVDOT;
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def VCMPGTUH : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtuh $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v8i16
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(PPCvcmp VRRC:$vA, VRRC:$vB, 582)))]>;
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def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v8i16
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@ -539,24 +539,23 @@ def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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// i32 element comparisons.
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def VCMPEQUW : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequw $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (PPCvcmp VRRC:$vA, VRRC:$vB, 134))]>;
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def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpequw. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4i32
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 134)))]>, isVDOT;
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def VCMPGTSW : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsw $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4i32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 902)))]>;
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def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4i32
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(PPCvcmp_o VRRC:$vA, VRRC:$vB, 902)))]>, isVDOT;
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def VCMPGTUW : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtuw $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD,
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(int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
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[(set VRRC:$vD, (v4i32
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(PPCvcmp VRRC:$vA, VRRC:$vB, 646)))]>;
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def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
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[(set VRRC:$vD, (v4i32
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@ -30,7 +30,7 @@ def SDT_PPCvperm : SDTypeProfile<1, 3, [
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SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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def SDT_PPCvcmp_o : SDTypeProfile<1, 3, [
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def SDT_PPCvcmp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
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]>;
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@ -71,7 +71,8 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
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def retflag : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
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[SDNPHasChain, SDNPOptInFlag]>;
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def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp_o, [SDNPOutFlag]>;
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def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
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def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// PowerPC specific transformation functions and pattern fragments.
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