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make intel asmprinter use TRI::getAsmName instead of TRI::getName like

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all the other targets.  Add support for weak/linkonce linkage so it doesn't
crash on basically all nontrivial testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2009-09-13 19:44:38 +00:00
parent cae05cb324
commit a1cb09e4b9
2 changed files with 21 additions and 15 deletions
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4
lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
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@@ -70,9 +70,7 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCOperand &Op = MI->getOperand(OpNo); const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) { if (Op.isReg()) {
O << '%'; O << '%' << TRI->getAsmName(Op.getReg());
unsigned Reg = Op.getReg();
O << TRI->getAsmName(Reg);
return; return;
} else if (Op.isImm()) { } else if (Op.isImm()) {
O << '$' << Op.getImm(); O << '$' << Op.getImm();

32
lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
View File

@@ -149,6 +149,11 @@ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
switch (F->getLinkage()) { switch (F->getLinkage()) {
default: llvm_unreachable("Unsupported linkage type!"); default: llvm_unreachable("Unsupported linkage type!");
case Function::LinkOnceAnyLinkage:
case Function::LinkOnceODRLinkage:
case Function::WeakAnyLinkage:
case Function::WeakODRLinkage:
case Function::PrivateLinkage: case Function::PrivateLinkage:
case Function::LinkerPrivateLinkage: case Function::LinkerPrivateLinkage:
case Function::InternalLinkage: case Function::InternalLinkage:
@@ -204,21 +209,24 @@ void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
} }
} }
static void PrintRegName(raw_ostream &O, StringRef RegName) {
for (unsigned i = 0, e = RegName.size(); i != e; ++i)
O << (char)toupper(RegName[i]);
}
void X86IntelAsmPrinter::printOp(const MachineOperand &MO, void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const char *Modifier) { const char *Modifier) {
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Register: { case MachineOperand::MO_Register: {
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ? EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 : MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 :
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8)); ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT); Reg = getX86SubSuperRegister(Reg, VT);
} }
O << TRI->getName(Reg); PrintRegName(O, TRI->getAsmName(Reg));
} else
O << "reg" << MO.getReg();
return; return;
} }
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
@@ -391,7 +399,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
break; break;
} }
O << TRI->getName(Reg); PrintRegName(O, TRI->getAsmName(Reg));
return false; return false;
} }