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Add SETEND and BXJ instructions for disassembly only.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96075 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-02-13 02:51:09 +00:00
parent cebe955779
commit a1e7621510
1 changed files with 28 additions and 0 deletions

28
lib/Target/ARM/ARMInstrInfo.td

@ -664,6 +664,26 @@ def CPS : AXI<(outs),(ins i32imm:$opt), MiscFrm, NoItinerary, "cps${opt:cps}",
let Inst{5} = 0;
}
def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM]> {
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010000;
let Inst{16} = 1;
let Inst{9} = 1;
let Inst{7-4} = 0b0000;
}
def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM]> {
let Inst{31-28} = 0b1111;
let Inst{27-20} = 0b00010000;
let Inst{16} = 1;
let Inst{9} = 0;
let Inst{7-4} = 0b0000;
}
def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV7]> {
@ -903,6 +923,14 @@ let isBranch = 1, isTerminator = 1 in {
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
}
// Branch and Exchange Jazelle -- for disassembly only
def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0010;
//let Inst{19-8} = 0xfff;
let Inst{7-4} = 0b0010;
}
// Supervisor call (software interrupt) -- for disassembly only
let isCall = 1 in {
def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",